| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | nv25.c | 42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000);
44 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000);
45 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000);
46 nvkm_wo32(chan->inst, 0x049c, 0x00000101);
47 nvkm_wo32(chan->inst, 0x04b0, 0x00000111);
48 nvkm_wo32(chan->inst, 0x04c8, 0x00000080);
49 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000);
50 nvkm_wo32(chan->inst, 0x04d0, 0x00000001);
51 nvkm_wo32(cha
[all...] |
| H A D | nv34.c | 42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101);
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111);
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060);
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080);
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001);
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000);
50 nvkm_wo32(chan->inst, 0x0480, 0xffff0000);
52 nvkm_wo32(cha
[all...] |
| H A D | nv35.c | 42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101);
44 nvkm_wo32(chan->inst, 0x0420, 0x00000111);
45 nvkm_wo32(chan->inst, 0x0424, 0x00000060);
46 nvkm_wo32(chan->inst, 0x0440, 0x00000080);
47 nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
48 nvkm_wo32(chan->inst, 0x0448, 0x00000001);
49 nvkm_wo32(chan->inst, 0x045c, 0x44400000);
50 nvkm_wo32(chan->inst, 0x0488, 0xffff0000);
52 nvkm_wo32(cha
[all...] |
| H A D | nv2a.c | 42 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
43 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
44 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
45 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
46 nvkm_wo32(chan->inst, 0x047c, 0x00000101);
47 nvkm_wo32(chan->inst, 0x0490, 0x00000111);
48 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
50 nvkm_wo32(chan->inst, i, 0x00030303);
52 nvkm_wo32(chan->inst, i, 0x00080000);
54 nvkm_wo32(cha
[all...] |
| H A D | nv30.c | 43 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
44 nvkm_wo32(chan->inst, 0x0410, 0x00000101);
45 nvkm_wo32(chan->inst, 0x0424, 0x00000111);
46 nvkm_wo32(chan->inst, 0x0428, 0x00000060);
47 nvkm_wo32(chan->inst, 0x0444, 0x00000080);
48 nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
49 nvkm_wo32(chan->inst, 0x044c, 0x00000001);
50 nvkm_wo32(chan->inst, 0x0460, 0x44400000);
51 nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
53 nvkm_wo32(cha
[all...] |
| H A D | nv20.c | 24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
54 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
96 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
97 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
98 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
99 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
100 nvkm_wo32(chan->inst, 0x047c, 0x00000101);
101 nvkm_wo32(chan->inst, 0x0490, 0x00000111);
102 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
104 nvkm_wo32(cha
[all...] |
| /linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| H A D | vmmgv100.c | 43 nvkm_wo32(inst, 0x21c, 0x00000000);
47 nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]);
48 nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]);
50 nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001);
51 nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001);
53 nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000);
56 nvkm_wo32(inst, 0x298, lower_32_bits(mask));
57 nvkm_wo32(inst, 0x29c, upper_32_bits(mask));
|
| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| H A D | usergf119.c | 50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000);
|
| H A D | usergv100.c | 50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
51 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start));
52 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start));
53 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit));
54 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit));
|
| H A D | usernv50.c | 51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
|
| H A D | usergf100.c | 51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
|
| H A D | usernv04.c | 65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
66 nvkm_wo32(*pgpuobj, 0x04, length);
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
|
| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | gv100.c | 47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd));
48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd));
49 nvkm_wo32(chan->inst, 0x010, 0x0000face);
50 nvkm_wo32(chan->inst, 0x030, 0x7ffff902);
51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset));
52 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16));
53 nvkm_wo32(chan->inst, 0x084, 0x20400000);
54 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm);
55 nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000);
56 nvkm_wo32(cha
[all...] |
| H A D | g84.c | 70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
71 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
72 nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);
73 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset));
74 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16));
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
77 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm);
78 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
81 nvkm_wo32(cha
[all...] |
| H A D | nv10.c | 45 nvkm_wo32(ramfc, base + 0x00, offset);
46 nvkm_wo32(ramfc, base + 0x04, offset);
47 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
48 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
|
| H A D | nv50.c | 103 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
104 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
105 nvkm_wo32(chan->ramfc, 0x48, chan->push->node->offset >> 4);
106 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(offset));
107 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(offset) | (limit2 << 16));
108 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
109 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
110 nvkm_wo32(chan->ramfc, 0x7c, 0x30000000 | devm);
111 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
194 nvkm_wo32(cha
[all...] |
| H A D | gf100.c | 91 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd));
92 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd));
93 nvkm_wo32(chan->inst, 0x10, 0x0000face);
94 nvkm_wo32(chan->inst, 0x30, 0xfffff902);
95 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset));
96 nvkm_wo32(chan->inst, 0x4c, upper_32_bits(offset) | (limit2 << 16));
97 nvkm_wo32(chan->inst, 0x54, 0x00000002);
98 nvkm_wo32(chan->inst, 0x84, 0x20400000);
99 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm);
100 nvkm_wo32(cha
[all...] |
| H A D | nv17.c | 46 nvkm_wo32(ramfc, base + 0x00, offset);
47 nvkm_wo32(ramfc, base + 0x04, offset);
48 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
49 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
|
| H A D | nv40.c | 47 nvkm_wo32(ramfc, base + 0x00, offset);
48 nvkm_wo32(ramfc, base + 0x04, offset);
49 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
50 nvkm_wo32(ramfc, base + 0x18, 0x30000000 |
57 nvkm_wo32(ramfc, base + 0x3c, 0x0001ffff);
160 nvkm_wo32(ramfc, chan->ramfc_offset + ctx, inst);
|
| H A D | gk104.c | 88 nvkm_wo32(chan->inst, 0x08, lower_32_bits(userd));
89 nvkm_wo32(chan->inst, 0x0c, upper_32_bits(userd));
90 nvkm_wo32(chan->inst, 0x10, 0x0000face);
91 nvkm_wo32(chan->inst, 0x30, 0xfffff902);
92 nvkm_wo32(chan->inst, 0x48, lower_32_bits(offset));
93 nvkm_wo32(chan->inst, 0x4c, upper_32_bits(offset) | (limit2 << 16));
94 nvkm_wo32(chan->inst, 0x84, 0x20400000);
95 nvkm_wo32(chan->inst, 0x94, 0x30000000 | devm);
96 nvkm_wo32(chan->inst, 0x9c, 0x00000100);
97 nvkm_wo32(cha
[all...] |
| H A D | gp100.c | 35 nvkm_wo32(memory, offset + 0, chan->id | chan->runq << 14);
36 nvkm_wo32(memory, offset + 4, chan->inst->addr >> 12);
|
| /linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | nv50.c | 156 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
157 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
158 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
159 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
161 nvkm_wo32(bar->bar2, 0x10, 0x00000000);
162 nvkm_wo32(bar->bar2, 0x14, 0x00000000);
192 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
193 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
194 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
195 nvkm_wo32(ba
[all...] |
| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/cipher/ |
| H A D | g84.c | 41 nvkm_wo32(*pgpuobj, 0x00, object->oclass);
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
|
| /linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| H A D | memory.h | 77 #define nvkm_wo32(o,a,d) (o)->ptrs->wr32((o), (a), (d)) macro
80 nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \
86 nvkm_wo32((o), __a + 0, lower_32_bits(__d)); \
87 nvkm_wo32((o), __a + 4, upper_32_bits(__d)); \
101 nvkm_wo32((o), _addr, *(_data++)); \
|
| /linux-master/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/ |
| H A D | nv50.c | 44 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1);
45 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c);
|