Searched refs:num_tile_cols (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/media/platform/verisilicon/
H A Dhantro_hevc.c77 unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1; local
81 if (num_tile_cols <= 1 ||
82 num_tile_cols <= hevc_dec->num_tile_cols_allocated)
107 size = (VERT_FILTER_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
115 size = (VERT_SAO_RAM_SIZE * height64 * (num_tile_cols - 1) * ctx->bit_depth) / 8;
123 size = BSD_CTRL_RAM_SIZE * height64 * (num_tile_cols - 1);
131 hevc_dec->num_tile_cols_allocated = num_tile_cols;
H A Dhantro_g2_hevc_dec.c19 unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1; local
44 vpu_debug(1, "Tiles enabled! %dx%d\n", num_tile_cols, num_tile_rows);
47 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols);
61 for (j = 0, tmp_w = 0; j < num_tile_cols - 1; j++) {
81 for (j = 0, prev_w = 0; j < num_tile_cols; j++) {
82 tmp = (j + 1) * pic_width_in_ctbs / num_tile_cols;
H A Drockchip_vpu981_hw_av1_dec.c260 unsigned int num_tile_cols = 1 << ctrls->tile_group_entry->tile_col; local
267 ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols)
272 size = ALIGN(height * 12 * ctx->bit_depth / 8, 128) * num_tile_cols;
280 size = ALIGN(height * 2 * 16 / 4, 128) * num_tile_cols;
288 size = ALIGN(height_in_sb * 44 * ctx->bit_depth * 16 / 8, 128) * num_tile_cols;
296 size = ALIGN(height_in_sb * (3040 + 1280), 128) * num_tile_cols;
304 size = ALIGN(stripe_num * 1536 * ctx->bit_depth / 8, 128) * num_tile_cols;
312 av1_dec->num_tile_cols_allocated = num_tile_cols;

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