Searched refs:num_levels (Results 1 - 25 of 63) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c122 clks->num_levels = 6;
127 clks->num_levels = 6;
132 clks->num_levels = 2;
137 clks->num_levels = 0;
224 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
226 dc_clks->num_levels = pp_clks->count;
231 for (i = 0; i < dc_clks->num_levels; i++) {
244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
247 pp_clks->num_levels,
250 clk_level_info->num_levels
[all...]
/linux-master/arch/arm64/kernel/
H A Dcacheinfo.c63 detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves);
94 this_cpu_ci->num_levels = level;
106 for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
/linux-master/drivers/video/backlight/
H A Dled_bl.c127 int num_levels; local
134 num_levels = of_property_count_u32_elems(node, "brightness-levels");
135 if (num_levels > 1) {
140 levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
147 num_levels);
156 for (i = 0 ; i < num_levels; i++) {
161 priv->max_brightness = num_levels - 1;
163 } else if (num_levels >= 0)
H A Dmp3309c.c208 unsigned int num_levels, tmp_value; local
242 num_levels = ANALOG_I2C_NUM_LEVELS;
255 num_levels = device_property_count_u32(dev, "brightness-levels");
256 if (num_levels < 2)
260 num_levels = MP3309C_PWM_DEFAULT_NUM_LEVELS;
265 pdata->levels = devm_kcalloc(dev, num_levels, sizeof(*pdata->levels), GFP_KERNEL);
270 pdata->levels, num_levels);
274 for (i = 0; i < num_levels; i++)
278 pdata->max_brightness = num_levels - 1;
H A Dpwm_bl.c233 unsigned int num_levels; local
262 num_levels = length / sizeof(u32);
265 if (num_levels > 0) {
266 data->levels = devm_kcalloc(dev, num_levels,
273 num_levels);
298 unsigned int num_input_levels = num_levels;
314 num_levels = (num_input_levels - 1) * num_steps + 1;
316 num_levels);
322 table = devm_kcalloc(dev, num_levels, sizeof(*table),
355 data->max_brightness = num_levels
[all...]
/linux-master/fs/verity/
H A Denable.c78 const int num_levels = params->num_levels; local
94 * Buffers 0 <= level < num_levels are for the actual tree levels.
95 * Buffer 'num_levels' is for the root hash.
97 for (level = -1; level < num_levels; level++) {
104 buffers[num_levels].data = root_hash;
105 buffers[num_levels].is_root_hash = true;
132 for (level = 0; level < num_levels; level++) {
158 for (level = 0; level < num_levels; level++) {
172 if (WARN_ON_ONCE(buffers[num_levels]
[all...]
H A Dopen.c103 * level to the starting block of that level. Level 'num_levels - 1' is
111 if (params->num_levels >= FS_VERITY_MAX_LEVELS) {
118 blocks_in_level[params->num_levels++] = blocks;
123 for (level = (int)params->num_levels - 1; level >= 0; level--) {
H A Dfsverity_private.h46 unsigned int num_levels; /* number of levels in Merkle tree */ member in struct:merkle_tree_params
52 * to root level ('num_levels - 1')
/linux-master/drivers/firmware/arm_scmi/
H A Dvoltage.c99 u32 num_levels; local
101 num_levels = num_returned + num_remaining;
106 if (!num_levels ||
110 num_levels, num_returned, num_remaining, v->id);
114 v->levels_uv = devm_kcalloc(dev, num_levels, sizeof(u32), GFP_KERNEL);
118 v->num_levels = num_levels;
152 /* Allocate space for num_levels if not already done */
153 if (!p->v->num_levels) {
158 st->max_resources = p->v->num_levels;
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c80 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) argument
88 *num_levels = 2;
91 /* will set num_levels to 0 on failure */
92 *num_levels = ret & 0xFF;
94 /* if the initial message failed, num_levels will be 0 */
95 for (i = 0; i < *num_levels; i++) {
111 unsigned int num_levels; local
134 &num_levels);
140 &num_levels);
145 &num_levels);
409 unsigned int num_levels; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c929 &eng_clks) || eng_clks.num_levels == 0) {
931 eng_clks.num_levels = 8;
934 for (i = 0; i < eng_clks.num_levels; i++) {
942 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
944 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
946 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
948 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
950 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
952 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
954 eng_clks.data[eng_clks.num_levels*
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c1090 clks.clocks_in_khz[clks.num_levels-1], 1000);
1092 clks.clocks_in_khz[clks.num_levels/8], 1000);
1094 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
1096 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1098 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1100 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1102 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1115 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier,
1118 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier,
1126 eng_clks.data[eng_clks.num_levels
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h98 uint32_t num_levels; member in struct:dm_pp_clock_levels
108 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_latency
118 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_voltage
/linux-master/drivers/gpu/drm/amd/include/
H A Ddm_pp_interface.h174 uint32_t num_levels; member in struct:pp_clock_levels_with_latency
184 uint32_t num_levels; member in struct:pp_clock_levels_with_voltage
/linux-master/drivers/gpu/drm/radeon/
H A Dr100_track.h44 unsigned num_levels; member in struct:r100_cs_track_texture
H A Dsumo_dpm.c345 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
352 for (i = 0; i < ps->num_levels - 1; i++)
406 for (i = 0; i < ps->num_levels; i++) {
407 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
421 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
422 CG_L(m_a * l[ps->num_levels - 1] / 100);
668 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
741 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
757 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
759 for (i = 0; i < new_ps->num_levels;
[all...]
H A Dtrinity_dpm.h48 u32 num_levels; member in struct:trinity_ps
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c133 unsigned int *num_levels)
142 *num_levels = 2;
145 /* will set num_levels to 0 on failure */
146 *num_levels = ret & 0xFF;
148 /* if the initial message failed, num_levels will be 0 */
149 for (i = 0; i < *num_levels; i++) {
165 unsigned int num_levels; local
213 num_levels = num_entries_per_clk->num_dispclk_levels;
223 num_levels = num_entries_per_clk->num_dppclk_levels;
235 for (i = 0; i < num_levels;
132 dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) argument
1019 unsigned int num_levels; local
[all...]
/linux-master/arch/s390/kernel/
H A Dcache.c142 this_cpu_ci->num_levels = level;
156 for (idx = 0, level = 0; level < this_cpu_ci->num_levels &&
/linux-master/arch/loongarch/kernel/
H A Dcacheinfo.c17 this_cpu_ci->num_levels =
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_wm.c151 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
191 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
309 if (ret != dev_priv->display.wm.num_levels)
314 for (level = 0; level < dev_priv->display.wm.num_levels; level++)
H A Di9xx_wm.c830 dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1;
937 for (; level < dev_priv->display.wm.num_levels; level++) {
956 for (; level < dev_priv->display.wm.num_levels; level++) {
986 for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
1056 if (level >= dev_priv->display.wm.num_levels)
1392 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1;
1398 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1;
1534 for (; level < dev_priv->display.wm.num_levels; level++) {
1563 for (; level < dev_priv->display.wm.num_levels; level++) {
1587 for (level = 0; level < dev_priv->display.wm.num_levels; leve
2966 int level, num_levels = dev_priv->display.wm.num_levels; local
[all...]
/linux-master/include/linux/
H A Dcacheinfo.h77 unsigned int num_levels; member in struct:cpu_cacheinfo
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c76 if (dc->sclk_lvls.num_levels == 0)
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
/linux-master/arch/mips/kernel/
H A Dcacheinfo.c53 this_cpu_ci->num_levels = levels;

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