Searched refs:num_heads (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/tegra/
H A Dhub.h48 unsigned int num_heads; member in struct:tegra_display_hub
H A Dhub.c973 unsigned int i = hub->num_heads;
1017 for (i = 0; i < hub->num_heads; i++) {
1120 hub->num_heads = of_get_child_count(pdev->dev.of_node);
1122 hub->clk_heads = devm_kcalloc(&pdev->dev, hub->num_heads, sizeof(clk),
1127 for (i = 0; i < hub->num_heads; i++) {
/linux-master/drivers/gpu/drm/qxl/
H A Dqxl_drv.c65 MODULE_PARM_DESC(num_heads, "Number of virtual crtcs to expose (default 4)");
66 module_param_named(num_heads, qxl_num_crtc, int, 0400);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c523 u32 num_heads; /* number of active crtcs */ member in struct:dce6_wm_params
716 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
717 (wm->num_heads * cursor_line_pair_return_time);
723 if (wm->num_heads == 0)
737 b.full = dfixed_const(wm->num_heads);
772 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
792 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
839 * @num_heads: number of display controllers in use
846 u32 lb_size, u32 num_heads)
860 if (amdgpu_crtc->base.enabled && num_heads
844 dce_v6_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) argument
1081 u32 num_heads = 0, lb_size; local
[all...]
H A Ddce_v11_0.c737 u32 num_heads; /* number of active crtcs */ member in struct:dce10_wm_params
930 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
931 (wm->num_heads * cursor_line_pair_return_time);
937 if (wm->num_heads == 0)
951 b.full = dfixed_const(wm->num_heads);
986 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1006 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1053 * @num_heads: number of display controllers in use
1060 u32 lb_size, u32 num_heads)
1069 if (amdgpu_crtc->base.enabled && num_heads
1058 dce_v11_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) argument
1193 u32 num_heads = 0, lb_size; local
[all...]
H A Ddce_v10_0.c705 u32 num_heads; /* number of active crtcs */ member in struct:dce10_wm_params
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899 (wm->num_heads * cursor_line_pair_return_time);
905 if (wm->num_heads == 0)
919 b.full = dfixed_const(wm->num_heads);
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1021 * @num_heads: number of display controllers in use
1028 u32 lb_size, u32 num_heads)
1037 if (amdgpu_crtc->base.enabled && num_heads
1026 dce_v10_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) argument
1161 u32 num_heads = 0, lb_size; local
[all...]
H A Ddce_v8_0.c658 u32 num_heads; /* number of active crtcs */ member in struct:dce8_wm_params
851 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
852 (wm->num_heads * cursor_line_pair_return_time);
858 if (wm->num_heads == 0)
872 b.full = dfixed_const(wm->num_heads);
907 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
927 (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
974 * @num_heads: number of display controllers in use
981 u32 lb_size, u32 num_heads)
990 if (amdgpu_crtc->base.enabled && num_heads
979 dce_v8_0_program_watermarks(struct amdgpu_device *adev, struct amdgpu_crtc *amdgpu_crtc, u32 lb_size, u32 num_heads) argument
1116 u32 num_heads = 0, lb_size; local
[all...]
/linux-master/fs/btrfs/
H A Ddelayed-ref.h190 unsigned long num_heads; member in struct:btrfs_delayed_ref_root
H A Ddelayed-ref.c674 delayed_refs->num_heads--;
949 delayed_refs->num_heads++;
/linux-master/drivers/gpu/drm/radeon/
H A Dsi.c2043 u32 num_heads; /* number of active crtcs */ member in struct:dce6_wm_params
2188 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2189 (wm->num_heads * cursor_line_pair_return_time);
2195 if (wm->num_heads == 0)
2209 b.full = dfixed_const(wm->num_heads);
2233 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2242 (dce6_available_bandwidth(wm) / wm->num_heads))
2276 u32 lb_size, u32 num_heads)
2290 if (radeon_crtc->base.enabled && num_heads && mode) {
2329 wm_high.num_heads
2274 dce6_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) argument
2444 u32 num_heads = 0, lb_size; local
[all...]
H A Devergreen.c1944 u32 num_heads; /* number of active crtcs */ member in struct:evergreen_wm_params
2072 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2073 (wm->num_heads * cursor_line_pair_return_time);
2078 if (wm->num_heads == 0)
2092 b.full = dfixed_const(wm->num_heads);
2114 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
2123 (evergreen_available_bandwidth(wm) / wm->num_heads))
2157 u32 lb_size, u32 num_heads)
2172 if (radeon_crtc->base.enabled && num_heads && mode) {
2207 wm_high.num_heads
2155 evergreen_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) argument
2328 u32 num_heads = 0, lb_size; local
[all...]
H A Dcik.c8908 u32 num_heads; /* number of active crtcs */ member in struct:dce8_wm_params
9101 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
9102 (wm->num_heads * cursor_line_pair_return_time);
9108 if (wm->num_heads == 0)
9122 b.full = dfixed_const(wm->num_heads);
9157 (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
9177 (dce8_available_bandwidth(wm) / wm->num_heads))
9224 * @num_heads: number of display controllers in use
9231 u32 lb_size, u32 num_heads)
9240 if (radeon_crtc->base.enabled && num_heads
9229 dce8_program_watermarks(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc, u32 lb_size, u32 num_heads) argument
9368 u32 num_heads = 0, lb_size; local
[all...]

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