Searched refs:mtable (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/net/ethernet/dec/tulip/
H A Deeprom.c120 tp->mtable = devm_kmalloc(&tp->pdev->dev, sizeof(struct mediatable) +
123 if (tp->mtable == NULL)
126 tp->mtable->defaultmedia = 0x800;
127 tp->mtable->leafcount = 1;
128 tp->mtable->csr12dir = 0x3f; /* inputs on bit7 for hsc-pci, bit6 for pci-fx */
129 tp->mtable->has_nonmii = 0;
130 tp->mtable->has_reset = 0;
131 tp->mtable->has_mii = 1;
132 tp->mtable->csr15dir = tp->mtable
211 struct mediatable *mtable; local
[all...]
H A Dtimer.c43 if (tp->mtable == NULL) { /* No EEPROM info, use generic code. */
53 mleaf = &tp->mtable->mleaf[tp->cur_index];
92 tp->cur_index = tp->mtable->leafcount - 1;
94 dev->if_port = tp->mtable->mleaf[tp->cur_index].media;
100 medianame[tp->mtable->mleaf[tp->cur_index].media]);
H A Dmedia.c171 struct mediatable *mtable = tp->mtable; local
175 if (mtable) {
176 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
185 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
199 if (startup && mtable->has_reset) {
200 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
285 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
324 if (startup && mtable
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H A D21142.c129 if (tp->mtable && tp->mtable->csr15dir) {
130 iowrite32(tp->mtable->csr15dir, ioaddr + CSR15);
131 iowrite32(tp->mtable->csr15val, ioaddr + CSR15);
186 if (tp->mtable) {
188 for (i = 0; i < tp->mtable->leafcount; i++)
189 if (tp->mtable->mleaf[i].media == dev->if_port) {
H A Dtulip_core.c303 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
373 if (tp->mtable == NULL)
378 for (i = 0; i < tp->mtable->leafcount; i++)
379 if (tp->mtable->mleaf[i].media == looking_for) {
386 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
387 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
388 for (i = 0; i < tp->mtable->leafcount; i++)
389 if (tp->mtable->mleaf[i].media == looking_for) {
397 for (i = tp->mtable
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H A Dtulip.h446 struct mediatable *mtable; member in struct:tulip_private
/linux-master/drivers/clk/renesas/
H A Drzg2l-cpg.h91 const u32 *mtable; member in struct:cpg_core_clk
170 .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier)
H A Drzg2l-cpg.c87 * @mtable: clock mux table
91 const u32 *mtable; member in struct:sd_mux_hw_data
475 val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index);
503 return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val);
529 sd_mux_hw_data->mtable = core->mtable;

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