Searched refs:mode_reg (Results 1 - 25 of 57) sorted by relevance

123

/linux-master/drivers/clk/qcom/
H A Dclk-pll.c31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
71 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
76 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
153 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
250 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 8);
259 qcom_pll_set_fsm_mode(regmap, pll->mode_reg, 1, 0);
269 ret = regmap_read(pll->clkr.regmap, pll->mode_reg,
[all...]
H A Dclk-hfpll.c67 regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
76 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
91 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
104 regmap_read(regmap, hd->mode_reg, &mode);
121 regmap_update_bits(regmap, hd->mode_reg,
213 regmap_read(regmap, hd->mode_reg, &mode);
239 regmap_read(regmap, hd->mode_reg, &mode);
H A Dclk-hfpll.h11 u32 mode_reg; member in struct:hfpll_data
H A Dhfpll.c18 .mode_reg = 0x00,
36 .mode_reg = 0x00,
53 .mode_reg = 0x00,
70 .mode_reg = 0x00,
H A Dclk-pll.h33 * @mode_reg: mode register
44 u32 mode_reg; member in struct:clk_pll
H A Da53-pll.c114 pll->mode_reg = 0x00;
/linux-master/drivers/regulator/
H A Dsy8824x.c22 unsigned int mode_reg; member in struct:sy8824_config
45 regmap_update_bits(rdev->regmap, cfg->mode_reg,
49 regmap_update_bits(rdev->regmap, cfg->mode_reg,
65 ret = regmap_read(rdev->regmap, cfg->mode_reg, &val);
168 .mode_reg = 0x00,
178 .mode_reg = 0x00,
188 .mode_reg = 0x01,
198 .mode_reg = 0x01,
H A Dfan53555.c141 unsigned int mode_reg; member in struct:fan53555_device_info
196 regmap_update_bits(rdev->regmap, di->mode_reg,
214 ret = regmap_read(rdev->regmap, di->mode_reg, &val);
502 di->mode_reg = FAN53555_CONTROL;
516 di->mode_reg = di->vol_reg;
524 di->mode_reg = FAN53555_VSEL1;
527 di->mode_reg = FAN53555_VSEL0;
532 di->mode_reg = TCS4525_COMMAND;
H A Drtq2134-regulator.c66 unsigned int mode_reg; member in struct:rtq2134_regulator_desc
91 return regmap_update_bits(rdev->regmap, desc->mode_reg, desc->mode_mask,
102 ret = regmap_read(rdev->regmap, desc->mode_reg, &mode);
296 .mode_reg = RTQ2134_REG_BUCK##_id##_DVS0CFG0, \
H A Dmt6360-regulator.c37 unsigned int mode_reg; member in struct:mt6360_regulator_desc
243 ret = regmap_update_bits(regmap, rdesc->mode_reg, rdesc->mode_mask, val << shift);
260 ret = regmap_read(regmap, rdesc->mode_reg, &val);
345 .mode_reg = mreg, \
H A Dpv88080-regulator.c34 unsigned int mode_reg; member in struct:pv88080_regulator
201 ret = regmap_read(rdev->regmap, info->mode_reg, &data);
242 return regmap_update_bits(rdev->regmap, info->mode_reg,
445 pv88080_regulator_info[i].mode_reg
H A Drtq2208-regulator.c78 unsigned int mode_reg; member in struct:rtq2208_regulator_desc
110 return regmap_update_bits(rdev->regmap, rdesc->mode_reg,
121 ret = regmap_read(rdev->regmap, rdesc->mode_reg, &mode_val);
424 rdesc->mode_reg = BUCK_RG_SHIFT(curr_info->base, 2);
/linux-master/drivers/clk/spear/
H A Dclk-vco-pll.c199 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
241 val = readl_relaxed(vco->mode_reg);
244 writel_relaxed(val, vco->mode_reg);
274 unsigned long flags, void __iomem *mode_reg, void __iomem
285 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
300 vco->mode_reg = mode_reg;
312 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
272 clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **pll_clk, struct clk **vco_gate_clk) argument
H A Dclk.h92 void __iomem *mode_reg; member in struct:clk_vco
122 unsigned long flags, void __iomem *mode_reg, void __iomem
/linux-master/drivers/net/can/ctucanfd/
H A Dctucanfd_base.c328 u32 mode_reg = ctucan_read32(priv, CTUCANFD_MODE); local
330 mode_reg = (mode->flags & CAN_CTRLMODE_LOOPBACK) ?
331 (mode_reg | REG_MODE_ILBP) :
332 (mode_reg & ~REG_MODE_ILBP);
334 mode_reg = (mode->flags & CAN_CTRLMODE_LISTENONLY) ?
335 (mode_reg | REG_MODE_BMM) :
336 (mode_reg & ~REG_MODE_BMM);
338 mode_reg = (mode->flags & CAN_CTRLMODE_FD) ?
339 (mode_reg | REG_MODE_FDE) :
340 (mode_reg
379 u32 mode_reg; local
[all...]
/linux-master/drivers/media/i2c/
H A Dlm3646.c64 * @mode_reg : mode register value
74 u8 mode_reg; member in struct:lm3646_flash
87 REG_ENABLE, flash->mode_reg | MODE_SHDN);
90 REG_ENABLE, flash->mode_reg | MODE_TORCH);
93 REG_ENABLE, flash->mode_reg | MODE_FLASH);
303 flash->mode_reg = reg_val & 0xfc;
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
H A Dtvnv04.c79 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
107 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head];
146 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
H A Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
464 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
556 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
557 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
559 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg
[all...]
H A Ddisp.h84 struct nv04_mode_state mode_reg; member in struct:nv04_display
H A Dcrtc.c67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
124 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
659 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
669 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
778 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
789 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
[all...]
/linux-master/sound/soc/sh/rcar/
H A Dssiu.c274 enum rsnd_reg adinr_reg, mode_reg, dalign_reg; local
278 mode_reg = SSI9_BUSIF_MODE(busif);
282 mode_reg = SSI_BUSIF_MODE(busif);
291 rsnd_mod_write(mod, mode_reg,
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-stm32.c92 u32 mode_reg; /* MAC glue-logic mode register */ member in struct:stm32_dwmac
163 u32 reg = dwmac->mode_reg, clk_rate;
224 u32 reg = dwmac->mode_reg;
288 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
/linux-master/drivers/mfd/
H A Dmenelaus.c441 u8 mode_reg; member in struct:menelaus_vtg
470 ret = menelaus_write_reg(vtg->mode_reg, mode);
564 .mode_reg = MENELAUS_LDO_CTRL3,
593 .mode_reg = MENELAUS_LDO_CTRL4,
633 .mode_reg = MENELAUS_DCDC_CTRL2,
641 .mode_reg = MENELAUS_DCDC_CTRL3,
678 .mode_reg = MENELAUS_LDO_CTRL7,
708 .mode_reg = MENELAUS_LDO_CTRL6,
/linux-master/drivers/net/ethernet/
H A Ddnet.c175 u32 mode_reg, ctl_reg; local
181 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG);
201 mode_reg |= DNET_INTERNAL_MODE_GBITEN;
205 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN;
220 mode_reg |=
223 mode_reg &=
236 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg);

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