Searched refs:mmio (Results 1 - 25 of 429) sorted by relevance

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/linux-master/sound/soc/au1x/
H A Dpsc.h13 void __iomem *mmio; member in struct:au1xpsc_audio_data
26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
34 #define AC97_PCR(x) ((x)->mmio
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/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-ufs.c41 void __iomem *mmio; member in struct:ufs_mtk_phy
62 void __iomem *mmio = phy->mmio; local
65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
77 mtk_phy_clear_bits(mmio
93 void __iomem *mmio = phy->mmio; local
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/linux-master/arch/riscv/include/asm/
H A Dclint.h10 #include <asm/mmio.h>
/linux-master/sound/pci/au88x0/
H A Dau88x0_mpu401.c16 /* Check for mpu401 mmio support. */
42 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) |
44 hwwrite(vortex->mmio, VORTEX_CTRL, temp);
48 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) &
50 hwwrite(vortex->mmio, VORTEX_CTRL, temp);
54 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf;
56 hwwrite(vortex->mmio, VORTEX_CTRL2, temp);
57 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET);
60 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA);
66 hwwrite(vortex->mmio, VORTEX_IRQ_CTR
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H A Dau88x0_xtalk.c248 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]);
249 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]);
250 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]);
251 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]);
252 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]);
254 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff);
255 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff);
265 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]);
266 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]);
267 hwwrite(vortex->mmio,
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H A Dau88x0_core.c79 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
114 a = hwread(vortex->mmio,
139 a = hwread(vortex->mmio,
143 hwwrite(vortex->mmio,
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H A Dau88x0_synth.c32 //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2));
33 temp = hwread(vortex->mmio, WT_STEREO(wt));
35 //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp);
36 hwwrite(vortex->mmio, WT_STEREO(wt), temp);
45 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0));
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp);
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000);
71 //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff);
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000);
74 //hwwrite(vortex->mmio, WT_GMOD
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H A Dau88x0_eq.c41 hwwrite(vortex->mmio, 0x2b3c4, gain);
42 hwwrite(vortex->mmio, 0x2b3c8, level);
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]);
61 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]);
64 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]);
65 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]);
66 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]);
68 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i]));
69 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i]));
70 hwwrite(vortex->mmio,
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/linux-master/drivers/bus/mhi/ep/
H A DMakefile2 mhi_ep-y := main.o mmio.o ring.o sm.o
/linux-master/tools/testing/selftests/kvm/lib/aarch64/
H A Ducall.c27 run->mmio.phys_addr == vcpu->vm->ucall_mmio_addr) {
28 TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(uint64_t),
29 "Unexpected ucall exit mmio address access");
30 return (void *)(*((uint64_t *)run->mmio.data));
/linux-master/drivers/misc/pvpanic/
H A DMakefile7 obj-$(CONFIG_PVPANIC_MMIO) += pvpanic.o pvpanic-mmio.o
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmmio.c14 val = readl(dev->mmio.regs + offset);
23 writel(val, dev->mmio.regs + offset);
36 __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));
42 __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));
74 spin_lock_irqsave(&dev->mmio.irq_lock, flags);
75 dev->mmio.irqmask &= ~clear;
76 dev->mmio.irqmask |= set;
78 if (mtk_wed_device_active(&dev->mmio.wed))
79 mtk_wed_device_irq_set_mask(&dev->mmio.wed,
80 dev->mmio
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/linux-master/drivers/gpu/drm/xe/
H A Dxe_irq.c33 static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg) argument
35 u32 val = xe_mmio_read32(mmio, reg);
40 drm_WARN(&gt_to_xe(mmio)->drm, 1,
43 xe_mmio_write32(mmio, reg, 0xffffffff);
44 xe_mmio_read32(mmio, reg);
45 xe_mmio_write32(mmio, reg, 0xffffffff);
46 xe_mmio_read32(mmio, reg);
55 struct xe_gt *mmio = tile->primary_gt; local
61 assert_iir_is_zero(mmio, IIR(irqregs));
63 xe_mmio_write32(mmio, IE
73 struct xe_gt *mmio = tile->primary_gt; local
90 struct xe_gt *mmio = xe_root_mmio_gt(xe); local
106 struct xe_gt *mmio = xe_root_mmio_gt(xe); local
121 struct xe_gt *mmio = xe_root_mmio_gt(xe); local
206 gt_engine_identity(struct xe_device *xe, struct xe_gt *mmio, const unsigned int bank, const unsigned int bit) argument
291 struct xe_gt *mmio = tile->primary_gt; local
377 struct xe_gt *mmio = xe_root_mmio_gt(xe); local
395 struct xe_gt *mmio = xe_root_mmio_gt(xe); local
432 struct xe_gt *mmio = tile->primary_gt; local
473 struct xe_gt *mmio = tile->primary_gt; local
546 struct xe_gt *mmio = tile->primary_gt; local
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H A Dxe_mmio.h31 if (reg.addr < gt->mmio.adj_limit)
32 reg.addr += gt->mmio.adj_offset;
34 return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);
41 if (reg.addr < gt->mmio.adj_limit)
42 reg.addr += gt->mmio.adj_offset;
44 return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);
52 if (reg.addr < gt->mmio.adj_limit)
53 reg.addr += gt->mmio.adj_offset;
55 writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);
62 if (reg.addr < gt->mmio
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/linux-master/drivers/mux/
H A DMakefile10 mux-mmio-objs := mmio.o
16 obj-$(CONFIG_MUX_MMIO) += mux-mmio.o
/linux-master/drivers/net/ethernet/amd/
H A Damd8111e.c101 void __iomem *mmio = lp->mmio; local
105 reg_val = readl(mmio + PHY_ACCESS);
107 reg_val = readl(mmio + PHY_ACCESS);
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS);
112 reg_val = readl(mmio + PHY_ACCESS);
131 void __iomem *mmio = lp->mmio; local
134 reg_val = readl(mmio + PHY_ACCESS);
136 reg_val = readl(mmio
368 void __iomem *mmio = lp->mmio; local
424 void __iomem *mmio = lp->mmio; local
502 void __iomem *mmio = lp->mmio; local
686 void __iomem *mmio = lp->mmio; local
835 amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) argument
858 void __iomem *mmio = lp->mmio; local
1082 void __iomem *mmio = lp->mmio; local
1296 void __iomem *mmio = lp->mmio; local
1646 void __iomem *mmio = lp->mmio; local
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/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dpci.h13 bool detect, bool mmio, u64 subdev_mask,
/linux-master/drivers/video/fbdev/i810/
H A Di810_main.c162 * @mmio: address of register space
168 static void i810_screen_off(u8 __iomem *mmio, u8 mode) argument
173 i810_writeb(SR_INDEX, mmio, SR01);
174 val = i810_readb(SR_DATA, mmio);
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
179 i810_writeb(SR_INDEX, mmio, SR01);
180 i810_writeb(SR_DATA, mmio, val);
185 * @mmio: address of register space
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode) argument
196 val = i810_readb(DRAMCH, mmio);
211 i810_protect_regs(u8 __iomem *mmio, int mode) argument
234 u8 __iomem *mmio = par->mmio_start_virtual; local
259 u8 __iomem *mmio = par->mmio_start_virtual; local
302 u8 __iomem *mmio = par->mmio_start_virtual; local
329 u8 __iomem *mmio = par->mmio_start_virtual; local
349 i810_hires(u8 __iomem *mmio) argument
372 u8 __iomem *mmio = par->mmio_start_virtual; local
402 u8 __iomem *mmio = par->mmio_start_virtual; local
424 u8 __iomem *mmio = par->mmio_start_virtual; local
441 i810_write_dac(u8 regno, u8 red, u8 green, u8 blue, u8 __iomem *mmio) argument
450 i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue, u8 __iomem *mmio) argument
465 u8 __iomem *mmio = par->mmio_start_virtual; local
485 u8 __iomem *mmio = par->mmio_start_virtual; local
497 u8 __iomem *mmio = par->mmio_start_virtual; local
531 u8 __iomem *mmio = par->mmio_start_virtual; local
546 u8 __iomem *mmio = par->mmio_start_virtual; local
560 u8 __iomem *mmio = par->mmio_start_virtual; local
589 u8 __iomem *mmio = par->mmio_start_virtual; local
612 u8 __iomem *mmio = par->mmio_start_virtual; local
636 u8 __iomem *mmio = par->mmio_start_virtual; local
650 u8 __iomem *mmio = par->mmio_start_virtual; local
773 i810_enable_cursor(u8 __iomem *mmio, int mode) argument
823 u8 __iomem *mmio = par->mmio_start_virtual; local
853 u8 __iomem *mmio = par->mmio_start_virtual; local
1204 u8 __iomem *mmio = par->mmio_start_virtual; local
1287 u8 __iomem *mmio = par->mmio_start_virtual; local
1393 u8 __iomem *mmio = par->mmio_start_virtual; local
1482 u8 __iomem *mmio = par->mmio_start_virtual; local
1821 u8 __iomem *mmio = par->mmio_start_virtual; local
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/linux-master/arch/m68k/virt/
H A Dconfig.c39 void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio;
49 void __iomem *base = (void __iomem *)virt_bi_data.ctrl.mmio;
71 virt_bi_data.pic.mmio = be32_to_cpup(data);
76 virt_bi_data.rtc.mmio = be32_to_cpup(data);
81 virt_bi_data.tty.mmio = be32_to_cpup(data);
86 virt_bi_data.ctrl.mmio = be32_to_cpup(data);
91 virt_bi_data.virtio.mmio = be32_to_cpup(data);
105 (void __iomem *)virt_bi_data.rtc.mmio);
113 virt_bi_data.tty.mmio);
117 DEFINE_RES_MEM_NAMED(virt_bi_data.ctrl.mmio,
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/linux-master/drivers/comedi/drivers/
H A Dni_pcidio.c311 dev->mmio + DMA_LINE_CONTROL_GROUP1);
327 dev->mmio + DMA_LINE_CONTROL_GROUP1);
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
394 flags = readb(dev->mmio + GROUP_1_FLAGS);
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
420 writeb(0x00, dev->mmio +
425 auxdata = readl(dev->mmio + GROUP_1_FIFO);
427 flags = readb(dev->mmio + GROUP_1_FLAGS);
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
435 writeb(0x00, dev->mmio
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H A Drtd520.c464 writel(0, dev->mmio + LAS0_CGT_CLEAR);
465 writel(1, dev->mmio + LAS0_CGT_ENABLE);
468 dev->mmio + LAS0_CGT_WRITE);
471 writel(0, dev->mmio + LAS0_CGT_ENABLE);
473 dev->mmio + LAS0_CGL_WRITE);
488 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
491 writel(0, dev->mmio + LAS0_ADC_CONVERSION);
496 writew(0, dev->mmio + LAS0_ADC);
498 fifo_status = readl(dev->mmio + LAS0_ADC);
508 writel(0, dev->mmio
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/linux-master/drivers/net/ethernet/cavium/liquidio/
H A Docteon_main.h98 if (oct->mmio[baridx].done)
99 iounmap(oct->mmio[baridx].hw_addr);
101 if (oct->mmio[baridx].start)
122 oct->mmio[baridx].start = pci_resource_start(oct->pci_dev, baridx * 2);
123 oct->mmio[baridx].len = pci_resource_len(oct->pci_dev, baridx * 2);
125 mapped_len = oct->mmio[baridx].len;
132 oct->mmio[baridx].hw_addr =
133 ioremap(oct->mmio[baridx].start, mapped_len);
134 oct->mmio[baridx].mapped_len = mapped_len;
137 baridx, oct->mmio[barid
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/linux-master/drivers/ata/
H A Dsata_sx4.c419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
428 mmio += PDC_CHIP0_OFS;
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
470 ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; local
484 mmio += PDC_CHIP0_OFS;
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
504 ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
532 mmio
597 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
655 pdc20621_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc, unsigned int doing_hdma, void __iomem *mmio) argument
795 void __iomem *mmio = ap->ioaddr.cmd_addr; local
809 void __iomem *mmio = ap->ioaddr.cmd_addr; local
826 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; local
943 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
993 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1038 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1097 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1160 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1218 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
1357 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; local
[all...]
/linux-master/drivers/mtd/nand/raw/brcmnand/
H A Diproc_nand.c36 void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET; local
37 u32 val = brcmnand_readl(mmio);
40 brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
51 void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; local
57 val = brcmnand_readl(mmio);
64 brcmnand_writel(val, mmio);
74 void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; local
80 val = brcmnand_readl(mmio);
96 brcmnand_writel(val, mmio);
/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-ipq806x-sata.c19 void __iomem *mmio; member in struct:qcom_ipq806x_sata_phy
59 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
63 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
70 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
79 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
85 reg = readl_relaxed(phy->mmio
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