Searched refs:mmVGT_ESGS_RING_SIZE_Sienna_Cichlid (Results 1 - 1 of 1) sorted by path
| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v10_0.c | 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 macro
6941 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6942 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6945 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6949 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7029 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
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