/linux-master/drivers/net/ethernet/mellanox/mlx4/ |
H A D | fw_qos.c | 103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, 151 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, 210 err = mlx4_cmd(dev, mailbox->dma, port, 280 err = mlx4_cmd(dev, mailbox->dma, (vport << 8) | port,
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H A D | srq.c | 67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, 82 return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ, 153 if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
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H A D | cq.c | 149 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, 157 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ, 281 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
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H A D | en_selftest.c | 45 return mlx4_cmd(priv->mdev->dev, 0, 0, 0, MLX4_CMD_HW_HEALTH_CHECK,
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H A D | mr.c | 239 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP, 279 return mlx4_cmd(dev, mailbox->dma, mpt_index, 435 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT, 473 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE, 517 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM, 971 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT,
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H A D | qp.c | 150 ret = mlx4_cmd(dev, 0, qp->qpn, 2, 187 ret = mlx4_cmd(dev, mailbox->dma, 301 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE, 388 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM, 509 err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0, 540 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
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H A D | port.c | 142 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 549 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 1195 err = mlx4_cmd(dev, mailbox->dma, 1469 err = mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod, 1476 return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod, 1532 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT, 1595 err = mlx4_cmd(dev, mailbox->dma, port, 1633 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 1671 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 1695 err = mlx4_cmd(de [all...] |
H A D | fw.c | 197 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 1566 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1577 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1607 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1614 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1621 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 2058 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 2272 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2282 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2336 err = mlx4_cmd(de [all...] |
H A D | icm.c | 243 return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM, 254 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX,
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H A D | pd.c | 108 err = mlx4_cmd(dev, in_param, RES_XRCD,
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H A D | mcg.c | 75 err = mlx4_cmd(dev, regid, 0, 0, 92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, 102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, 1096 err = mlx4_cmd(dev, in_param, 0, 0, 1356 err = mlx4_cmd(dev, mailbox->dma, qpn, attach, 1584 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
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H A D | eq.c | 485 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 891 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 905 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 913 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 920 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
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H A D | resource_tracker.c | 3390 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0, 4336 err = mlx4_cmd(dev, inbox->dma, 4477 mlx4_cmd(dev, vhcr->out_param, 0, 0, 4495 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH, 4550 err = mlx4_cmd(dev, vhcr->in_param, 0, 0, 4708 err = mlx4_cmd(dev, in_param, 4774 err = mlx4_cmd(dev, in_param, srqn, 1, 4839 err = mlx4_cmd(dev, in_param, cqn, 1, 4906 err = mlx4_cmd(dev, in_param, mptn, 0, 5020 mlx4_cmd(de [all...] |
H A D | en_dcb_nl.c | 653 err = mlx4_cmd(priv->mdev->dev, mailbox_in_dma, inmod,
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H A D | en_port.c | 66 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
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H A D | mlx4.h | 630 struct mlx4_cmd { struct 896 struct mlx4_cmd cmd;
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H A D | cmd.c | 341 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 436 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 681 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 808 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL, 2532 priv->cmd.pool = dma_pool_create("mlx4_cmd",
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H A D | main.c | 2682 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
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/linux-master/include/linux/mlx4/ |
H A D | cmd.h | 273 static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, function
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/linux-master/drivers/infiniband/hw/mlx4/ |
H A D | main.c | 179 err = mlx4_cmd(dev, mailbox->dma, 184 err += mlx4_cmd(dev, mailbox->dma, 224 err = mlx4_cmd(dev, mailbox->dma, 229 err += mlx4_cmd(dev, mailbox->dma, 1025 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0, 1051 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE, 1604 err = mlx4_cmd(dev, reg_id, 0, 0,
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