Searched refs:mlx4_cmd (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/net/ethernet/mellanox/mlx4/
H A Dfw_qos.c103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
151 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
210 err = mlx4_cmd(dev, mailbox->dma, port,
280 err = mlx4_cmd(dev, mailbox->dma, (vport << 8) | port,
H A Dsrq.c67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0,
82 return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
153 if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
H A Dcq.c149 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod,
157 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
281 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
H A Den_selftest.c45 return mlx4_cmd(priv->mdev->dev, 0, 0, 0, MLX4_CMD_HW_HEALTH_CHECK,
H A Dmr.c239 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
279 return mlx4_cmd(dev, mailbox->dma, mpt_index,
435 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
473 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
517 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
971 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT,
H A Dqp.c150 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
187 ret = mlx4_cmd(dev, mailbox->dma,
301 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
388 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
509 err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
540 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
H A Dport.c142 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
549 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1195 err = mlx4_cmd(dev, mailbox->dma,
1469 err = mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
1476 return mlx4_cmd(dev, inbox->dma, in_mod & 0xffff, op_mod,
1532 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
1595 err = mlx4_cmd(dev, mailbox->dma, port,
1633 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1671 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
1695 err = mlx4_cmd(de
[all...]
H A Dfw.c197 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
1566 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1577 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1607 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1614 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1621 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
2058 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
2272 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2282 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2336 err = mlx4_cmd(de
[all...]
H A Dicm.c243 return mlx4_cmd(dev, virt, page_count, 0, MLX4_CMD_UNMAP_ICM,
254 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_ICM_AUX,
H A Dpd.c108 err = mlx4_cmd(dev, in_param, RES_XRCD,
H A Dmcg.c75 err = mlx4_cmd(dev, regid, 0, 0,
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
1096 err = mlx4_cmd(dev, in_param, 0, 0,
1356 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1584 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
H A Deq.c485 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
891 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
905 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
913 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
920 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
H A Dresource_tracker.c3390 err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
4336 err = mlx4_cmd(dev, inbox->dma,
4477 mlx4_cmd(dev, vhcr->out_param, 0, 0,
4495 mlx4_cmd(dev, fs_rule->com.res_id, 0, 0, MLX4_QP_FLOW_STEERING_DETACH,
4550 err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
4708 err = mlx4_cmd(dev, in_param,
4774 err = mlx4_cmd(dev, in_param, srqn, 1,
4839 err = mlx4_cmd(dev, in_param, cqn, 1,
4906 err = mlx4_cmd(dev, in_param, mptn, 0,
5020 mlx4_cmd(de
[all...]
H A Den_dcb_nl.c653 err = mlx4_cmd(priv->mdev->dev, mailbox_in_dma, inmod,
H A Den_port.c66 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR,
H A Dmlx4.h630 struct mlx4_cmd { struct
896 struct mlx4_cmd cmd;
H A Dcmd.c341 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
436 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
681 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
808 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
2532 priv->cmd.pool = dma_pool_create("mlx4_cmd",
H A Dmain.c2682 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
/linux-master/include/linux/mlx4/
H A Dcmd.h273 static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, function
/linux-master/drivers/infiniband/hw/mlx4/
H A Dmain.c179 err = mlx4_cmd(dev, mailbox->dma,
184 err += mlx4_cmd(dev, mailbox->dma,
224 err = mlx4_cmd(dev, mailbox->dma,
229 err += mlx4_cmd(dev, mailbox->dma,
1025 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1051 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1604 err = mlx4_cmd(dev, reg_id, 0, 0,

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