Searched refs:min_clocks (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.c1610 struct PP_Clocks min_clocks = {0}; local
1620 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1621 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1622 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1626 clock_req.clock_freq_in_khz = min_clocks.dcefClock / 10;
1632 min_clocks.dcefClockInSR / 100,
H A Dvega20_hwmgr.c2343 struct PP_Clocks min_clocks = {0}; local
2347 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2348 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2349 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2353 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2358 min_clocks.dcefClockInSR / 100,
2368 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
H A Dvega10_hwmgr.c4069 struct PP_Clocks min_clocks = {0}; local
4080 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4081 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4082 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4085 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4095 min_clocks.dcefClockInSR / 100,
4104 if (min_clocks.memoryClock != 0) {
4105 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
H A Dsmu7_hwmgr.c4090 struct PP_Clocks min_clocks = {0}; local
4107 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4108 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c2077 struct smu_clocks min_clocks = {0}; local
2081 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2082 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2083 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2087 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2094 min_clocks.dcef_clock_in_sr/100,
2107 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
H A Dsienna_cichlid_ppt.c1793 struct smu_clocks min_clocks = {0}; local
1797 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1798 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1799 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1803 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1810 min_clocks.dcef_clock_in_sr/100,
1823 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);

Completed in 227 milliseconds