Searched refs:masks (Results 1 - 25 of 182) sorted by relevance

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/linux-master/drivers/clk/mmp/
H A Dclk-frac.c35 do_div(rate, factor->ftbl[i].num * factor->masks->factor);
54 struct mmp_clk_factor_masks *masks = factor->masks; local
61 num = (val >> masks->num_shift) & masks->num_mask;
64 den = (val >> masks->den_shift) & masks->den_mask;
71 do_div(rate, num * factor->masks->factor);
81 struct mmp_clk_factor_masks *masks = factor->masks; local
120 struct mmp_clk_factor_masks *masks = factor->masks; local
168 mmp_clk_register_factor(const char *name, const char *parent_name, unsigned long flags, void __iomem *base, struct mmp_clk_factor_masks *masks, struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt, spinlock_t *lock) argument
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/linux-master/block/
H A Dblk-mq-cpumap.c20 const struct cpumask *masks; local
23 masks = group_cpus_evenly(qmap->nr_queues);
24 if (!masks) {
31 for_each_cpu(cpu, &masks[queue])
34 kfree(masks);
/linux-master/lib/
H A Dgroup_cpus.c47 cpumask_var_t *masks; local
50 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL);
51 if (!masks)
55 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL))
59 return masks;
63 free_cpumask_var(masks[node]);
64 kfree(masks);
68 static void free_node_to_cpumask(cpumask_var_t *masks) argument
73 free_cpumask_var(masks[node]);
74 kfree(masks);
77 build_node_to_cpumask(cpumask_var_t *masks) argument
249 __group_cpus_evenly(unsigned int startgrp, unsigned int numgrps, cpumask_var_t *node_to_cpumask, const struct cpumask *cpu_mask, struct cpumask *nmsk, struct cpumask *masks) argument
353 struct cpumask *masks = NULL; local
429 struct cpumask *masks = kcalloc(numgrps, sizeof(*masks), GFP_KERNEL); local
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/linux-master/arch/arm/mach-s3c/
H A Dwakeup-mask.h27 * @masks: The list of masks to use.
28 * @nr_masks: The number of entries pointed to buy @masks.
31 * of interrupts and control bits in @masks. We do this at suspend time
36 const struct samsung_wakeup_mask *masks,
/linux-master/drivers/clk/spear/
H A Dclk-aux-synth.c77 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
78 if (eqn == aux->masks->eq1_mask)
82 num = (val >> aux->masks->xscale_sel_shift) &
83 aux->masks->xscale_sel_mask;
86 den *= (val >> aux->masks->yscale_sel_shift) &
87 aux->masks->yscale_sel_mask;
111 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
112 val |= (rtbl[i].eq & aux->masks
134 clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) argument
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/linux-master/kernel/irq/
H A Daffinity.c19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
29 struct irq_affinity_desc *masks = NULL; local
59 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL);
60 if (!masks)
65 cpumask_copy(&masks[curvec].mask, irq_default_affinity);
77 kfree(masks);
82 cpumask_copy(&masks[curvec + j].mask, &result[j]);
95 cpumask_copy(&masks[curvec].mask, irq_default_affinity);
99 masks[
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_generic.h36 const struct generic_sh_mask *masks; member in struct:hw_generic
H A Dhw_ddc.h35 const struct ddc_sh_mask *masks; member in struct:hw_ddc
H A Dhw_hpd.h35 const struct hpd_sh_mask *masks; member in struct:hw_hpd
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/
H A Dpedit.h20 struct pedit_headers masks; member in struct:pedit_headers_action
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
H A Ddcn301_hwseq.c40 hws->shifts->field_name, hws->masks->field_name
/linux-master/drivers/clk/uniphier/
H A Dclk-uniphier-mux.c17 const unsigned int *masks; member in struct:uniphier_clk_mux
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
44 if ((mux->masks[i] & val) == mux->vals[i])
77 mux->masks = data->masks;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_hwseq.c43 hws->shifts->field_name, hws->masks->field_name
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_hubbub.c38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
79 hubbub3->masks = hubbub_mask;
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_i2c_hw.c41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
287 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
311 if (dce_i2c_hw->masks->DC_I2C_DDC1_CLK_EN)
626 const struct dce_i2c_mask *masks)
633 dce_i2c_hw->masks = masks;
620 dce_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
643 dce100_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
660 dce112_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
677 dcn1_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
694 dcn2_i2c_hw_construct( struct dce_i2c_hw *dce_i2c_hw, struct dc_context *ctx, uint32_t engine_id, const struct dce_i2c_registers *regs, const struct dce_i2c_shift *shifts, const struct dce_i2c_mask *masks) argument
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/linux-master/tools/perf/trace/beauty/
H A Dprctl.c65 const u8 masks[] = { local
78 if (option < ARRAY_SIZE(masks))
79 arg->mask |= masks[option];
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_hubbub.c41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
103 hubbub->masks = hubbub_mask;
/linux-master/arch/powerpc/include/asm/nohash/32/
H A Dpte-40x.h70 #include <asm/pgtable-masks.h>
H A Dpte-44x.h103 #include <asm/pgtable-masks.h>
H A Dpte-85xx.h59 #include <asm/pgtable-masks.h>
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp_cm.c174 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;
176 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;
179 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;
181 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;
183 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;
185 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;
188 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;
190 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;
192 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;
194 reg->masks
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H A Ddcn30_dwb_cm.c53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B;
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
73 reg->masks
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/linux-master/drivers/net/dsa/microchip/
H A Dksz8795.c165 const u32 *masks; local
172 masks = dev->info->masks;
187 if (check & masks[MIB_COUNTER_VALID]) {
189 if (check & masks[MIB_COUNTER_OVERFLOW])
201 const u32 *masks; local
208 masks = dev->info->masks;
225 if (check & masks[MIB_COUNTER_VALID]) {
234 if (check & masks[MIB_COUNTER_OVERFLO
386 const u32 *masks; local
416 const u32 *masks; local
479 const u32 *masks; local
531 const u32 *masks; local
563 const u32 *masks; local
578 const u32 *masks; local
1514 const u32 *masks; local
1562 const u32 *masks; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_cm_common.h71 struct xfer_func_mask masks; member in struct:xfer_func_reg
86 struct cm_color_matrix_mask masks; member in struct:color_matrices_reg
H A Ddcn10_dpp_cm.c119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
197 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
199 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
282 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
284 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
329 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
331 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
333 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
335 reg->masks
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