/linux-master/tools/testing/selftests/bpf/progs/ |
H A D | cpumask_success.c | 27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; local 29 mask1 = create_cpumask(); 30 if (!mask1) 35 bpf_cpumask_release(mask1); 42 bpf_cpumask_release(mask1); 50 bpf_cpumask_release(mask1); 57 *out1 = mask1; 181 struct bpf_cpumask *mask1, *mask2; local 187 mask1 = create_cpumask(); 188 if (!mask1) 245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local 292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local 334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; local 510 struct bpf_cpumask *mask1, *mask2; local [all...] |
/linux-master/arch/parisc/kernel/ |
H A D | sys_parisc32.c | 28 compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, 32 ((__u64)mask1 << 32) | mask0, 27 sys32_fanotify_mark(compat_int_t fanotify_fd, compat_uint_t flags, compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, const char __user * pathname) argument
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/linux-master/sound/pci/ice1712/ |
H A D | wm8776.c | 135 .mask1 = WM8776_DACVOL_MASK, 145 .mask1 = WM8776_DAC_PL_LL, 153 .mask1 = WM8776_DAC_DZCEN, 161 .mask1 = WM8776_HPVOL_MASK, 171 .mask1 = WM8776_PWR_HPPD, 179 .mask1 = WM8776_VOL_HPZCEN, 187 .mask1 = WM8776_OUTMUX_AUX, 193 .mask1 = WM8776_OUTMUX_BYPASS, 199 .mask1 = WM8776_DAC_IZD, 206 .mask1 [all...] |
H A D | wm8766.c | 36 .mask1 = WM8766_VOL_MASK, 47 .mask1 = WM8766_VOL_MASK, 58 .mask1 = WM8766_VOL_MASK, 67 .mask1 = WM8766_DAC2_MUTE1, 74 .mask1 = WM8766_DAC2_MUTE2, 81 .mask1 = WM8766_DAC2_MUTE3, 88 .mask1 = WM8766_PHASE_INVERT1, 94 .mask1 = WM8766_PHASE_INVERT2, 100 .mask1 = WM8766_PHASE_INVERT3, 106 .mask1 [all...] |
/linux-master/drivers/gpu/drm/amd/display/dmub/src/ |
H A D | dmub_reg.c | 45 uint32_t mask1, uint32_t field_value1, 52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, 73 uint32_t mask1, uint32_t field_value1, ...) 80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) 96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 43 set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) argument 72 dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument 89 dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument
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/linux-master/drivers/ras/amd/atl/ |
H A D | system.c | 56 static void df3_get_masks_shifts(u32 mask0, u32 mask1) argument 61 df_cfg.node_id_shift = FIELD_GET(DF3_NODE_ID_SHIFT, mask1); 62 df_cfg.socket_id_shift = FIELD_GET(DF3_SOCKET_ID_SHIFT, mask1); 63 df_cfg.socket_id_mask = FIELD_GET(DF3_SOCKET_ID_MASK, mask1); 64 df_cfg.die_id_mask = FIELD_GET(DF3_DIE_ID_MASK, mask1); 67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) argument 72 df_cfg.node_id_shift = FIELD_GET(DF3_NODE_ID_SHIFT, mask1); 73 df_cfg.socket_id_shift = FIELD_GET(DF4_SOCKET_ID_SHIFT, mask1); 79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) argument 81 df3p5_get_masks_shifts(mask0, mask1, mask 96 u32 mask0, mask1, mask2; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_helper.c | 113 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 121 field_value1, mask1, shift1); 228 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 237 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 256 uint8_t shift1, uint32_t mask1, uint32_t field_value1, 264 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 292 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 296 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); 302 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, 307 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift 111 set_reg_field_values(struct dc_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) argument 226 generic_reg_update_ex(const struct dc_context *ctx, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument 254 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument 291 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) argument 301 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) argument 313 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) argument 327 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) argument 343 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) argument 361 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) argument 381 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) argument 511 generic_indirect_reg_get(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...) argument 542 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument 573 generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument 602 generic_indirect_reg_get_sync(const struct dc_context *ctx, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...) argument [all...] |
/linux-master/arch/alpha/kernel/ |
H A D | sys_rawhide.c | 102 unsigned int mask, mask1, hose; local 111 mask1 = 1 << irq; 112 mask = ~mask1 | hose_irq_masks[hose]; 121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1;
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H A D | sys_titan.c | 70 unsigned long mask0, mask1, mask2, mask3, dummy; 75 mask1 = mask & titan_cpu_irq_affinity[1]; 80 else if (bcpu == 1) mask1 |= isa_enable; 94 *dim1 = mask1; 69 unsigned long mask0, mask1, mask2, mask3, dummy; local
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/linux-master/arch/mips/sgi-ip27/ |
H A D | ip27-nmi.c | 127 u64 mask0, mask1, pend0, pend1; local 131 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); 134 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); 140 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1);
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
H A D | irq_service_dcn32.c | 209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 226 reg1 ## __ ## mask1 ## _MASK,\ 228 reg1 ## __ ## mask1 ## _MASK,\ 229 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
H A D | irq_service_dcn35.c | 207 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ 210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \ 221 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ 224 reg1 ## __ ## mask1 ## _MASK,\ 226 reg1 ## __ ## mask1 ## _MASK,\ 228 ~reg1 ## __ ## mask1 ## _MASK, \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
H A D | irq_service_dcn315.c | 215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 232 reg1 ## __ ## mask1 ## _MASK,\ 234 reg1 ## __ ## mask1 ## _MASK,\ 235 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
H A D | irq_service_dcn302.c | 195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 216 reg1 ## __ ## mask1 ## _MASK,\ 218 reg1 ## __ ## mask1 ## _MASK,\ 219 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
H A D | irq_service_dcn30.c | 220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 237 reg1 ## __ ## mask1 ## _MASK,\ 239 reg1 ## __ ## mask1 ## _MASK,\ 240 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
H A D | irq_service_dcn31.c | 208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 225 reg1 ## __ ## mask1 ## _MASK,\ 227 reg1 ## __ ## mask1 ## _MASK,\ 228 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
H A D | irq_service_dcn314.c | 210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 227 reg1 ## __ ## mask1 ## _MASK,\ 229 reg1 ## __ ## mask1 ## _MASK,\ 230 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
H A D | irq_service_dcn21.c | 213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 219 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 227 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ 230 reg1 ## __ ## mask1 ## _MASK,\ 232 reg1 ## __ ## mask1 ## _MASK,\ 233 ~reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
H A D | irq_service_dcn351.c | 186 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ 189 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 191 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 193 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK, \ 200 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ 203 reg1 ## __ ## mask1 ## _MASK,\ 205 reg1 ## __ ## mask1 ## _MASK,\ 207 ~reg1 ## __ ## mask1 ## _MASK, \
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/linux-master/fs/orangefs/ |
H A D | orangefs-debugfs.c | 63 __u64 mask1; member in struct:client_debug_mask 456 c_mask.mask1, 543 (unsigned long long *)&(cdm_array[i].mask1), 755 if ((mask->mask1 & cdm_array[index].mask1) || 799 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && 806 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && 875 (**sane_mask).mask1 [all...] |
/linux-master/lib/ |
H A D | cpumask_kunit.c | 26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ 28 const cpumask_t *m1 = (mask1); \ 34 for_each_cpu_##op(cpu, mask1, mask2) \
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/linux-master/drivers/soc/fsl/qe/ |
H A D | gpio.c | 241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); local 260 if (sregs->cpdata & mask1) 261 qe_gc->cpdata |= mask1; 263 qe_gc->cpdata &= ~mask1; 266 qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
H A D | irq_service_dcn201.c | 152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 155 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 158 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
H A D | irq_service_dcn303.c | 138 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 140 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 142 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 143 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
H A D | irq_service_dcn10.c | 200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
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