Searched refs:lane_width (Results 1 - 13 of 13) sorted by relevance
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | hwmgr_ppt.h | 97 uint8_t lane_width; member in struct:phm_ppt_v1_pcie_record
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H A D | vega10_hwmgr.c | 1274 bios_pcie_table->entries[i].lane_width); 4654 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local 4728 lane_width = pptable->PcieLaneCount[i]; 4735 (lane_width == 1) ? "x1" : 4736 (lane_width == 2) ? "x2" : 4737 (lane_width == 3) ? "x4" : 4738 (lane_width == 4) ? "x8" : 4739 (lane_width == 5) ? "x12" : 4740 (lane_width == 6) ? "x16" : "", 4742 (current_lane_width == lane_width) 4800 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local [all...] |
H A D | vega20_hwmgr.c | 3369 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local 3463 lane_width = pptable->PcieLaneCount[i]; 3470 (lane_width == 1) ? "x1" : 3471 (lane_width == 2) ? "x2" : 3472 (lane_width == 3) ? "x4" : 3473 (lane_width == 4) ? "x8" : 3474 (lane_width == 5) ? "x12" : 3475 (lane_width == 6) ? "x16" : "", 3478 (current_lane_width == lane_width) ?
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H A D | process_pptables_v1_0.c | 519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); 557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth);
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H A D | vega10_processpptables.c | 815 pcie_table->entries[i].lane_width =
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H A D | smu7_hwmgr.c | 677 pcie_table->entries[i].lane_width));
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
H A D | arcturus_ppt.c | 766 uint32_t gen_speed, lane_width; local 854 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 889 (lane_width == 1) ? "x1" : 890 (lane_width == 2) ? "x2" : 891 (lane_width == 3) ? "x4" : 892 (lane_width == 4) ? "x8" : 893 (lane_width == 5) ? "x12" : 894 (lane_width == 6) ? "x16" : "",
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H A D | navi10_ppt.c | 1263 uint32_t gen_speed, lane_width; local 1334 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1349 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? 1470 uint32_t gen_speed, lane_width; local 1534 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1549 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
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H A D | sienna_cichlid_ppt.c | 1290 uint32_t gen_speed, lane_width; local 1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 1367 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
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/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
H A D | smu_v13_0_7_ppt.c | 1199 uint32_t gen_speed, lane_width; local 1299 &lane_width); 1318 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
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H A D | smu_v13_0_0_ppt.c | 1210 uint32_t gen_speed, lane_width; local 1310 &lane_width); 1329 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 5183 u32 lane_width; local 5254 lane_width = amdgpu_get_pcie_lanes(adev); 5255 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6395 u32 lane_width; local 6403 lane_width = amdgpu_get_pcie_lanes(adev); 6404 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | si_dpm.c | 4637 u32 lane_width; local 4708 lane_width = radeon_get_pcie_lanes(rdev); 4709 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5854 u32 lane_width; local 5862 lane_width = radeon_get_pcie_lanes(rdev); 5863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
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