Searched refs:lane_width (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h97 uint8_t lane_width; member in struct:phm_ppt_v1_pcie_record
H A Dvega10_hwmgr.c1274 bios_pcie_table->entries[i].lane_width);
4654 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local
4728 lane_width = pptable->PcieLaneCount[i];
4735 (lane_width == 1) ? "x1" :
4736 (lane_width == 2) ? "x2" :
4737 (lane_width == 3) ? "x4" :
4738 (lane_width == 4) ? "x8" :
4739 (lane_width == 5) ? "x12" :
4740 (lane_width == 6) ? "x16" : "",
4742 (current_lane_width == lane_width)
4800 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local
[all...]
H A Dvega20_hwmgr.c3369 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; local
3463 lane_width = pptable->PcieLaneCount[i];
3470 (lane_width == 1) ? "x1" :
3471 (lane_width == 2) ? "x2" :
3472 (lane_width == 3) ? "x4" :
3473 (lane_width == 4) ? "x8" :
3474 (lane_width == 5) ? "x12" :
3475 (lane_width == 6) ? "x16" : "",
3478 (current_lane_width == lane_width) ?
H A Dprocess_pptables_v1_0.c519 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth);
557 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth);
H A Dvega10_processpptables.c815 pcie_table->entries[i].lane_width =
H A Dsmu7_hwmgr.c677 pcie_table->entries[i].lane_width));
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Darcturus_ppt.c766 uint32_t gen_speed, lane_width; local
854 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
889 (lane_width == 1) ? "x1" :
890 (lane_width == 2) ? "x2" :
891 (lane_width == 3) ? "x4" :
892 (lane_width == 4) ? "x8" :
893 (lane_width == 5) ? "x12" :
894 (lane_width == 6) ? "x16" : "",
H A Dnavi10_ppt.c1263 uint32_t gen_speed, lane_width; local
1334 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1349 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1470 uint32_t gen_speed, lane_width; local
1534 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1549 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
H A Dsienna_cichlid_ppt.c1290 uint32_t gen_speed, lane_width; local
1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1367 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c1199 uint32_t gen_speed, lane_width; local
1299 &lane_width);
1318 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
H A Dsmu_v13_0_0_ppt.c1210 uint32_t gen_speed, lane_width; local
1310 &lane_width);
1329 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5183 u32 lane_width; local
5254 lane_width = amdgpu_get_pcie_lanes(adev);
5255 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6395 u32 lane_width; local
6403 lane_width = amdgpu_get_pcie_lanes(adev);
6404 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
/linux-master/drivers/gpu/drm/radeon/
H A Dsi_dpm.c4637 u32 lane_width; local
4708 lane_width = radeon_get_pcie_lanes(rdev);
4709 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5854 u32 lane_width; local
5862 lane_width = radeon_get_pcie_lanes(rdev);
5863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);

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