/linux-master/arch/mips/mm/ |
H A D | cex-gen.S | 30 mfc0 k0,CP0_CONFIG 32 and k0,k0,k1 33 ori k0,k0,CONF_CM_UNCACHED 34 mtc0 k0,CP0_CONFIG
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H A D | cex-sb1.S | 35 * (0x170-0x17f) are used to preserve k0, k1, and ra. 42 * save/restore k0 and k1 from low memory (Useg is direct 48 sd k0,0x170($0) 61 sll k0,k1,1 73 * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31. Any 81 bltz k0,unrecoverable 82 sll k0,1 85 * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31. If an 89 bgez k0,unrecoverable 97 mfc0 k0,C0_CERR_ [all...] |
H A D | cex-oct.S | 30 rdhwr k0, $0 /* get core_id */ 32 sll k0, k0, 3 33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ 35 dmfc0 k0, CP0_CACHEERR, 1 36 sd k0, (k1)
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/linux-master/arch/mips/kernel/ |
H A D | bmips_vec.S | 41 la k0, 1f 43 or k0, k1 44 jr k0 51 li k0, ST0_IE | ST0_BEV | STATUSF_IP1 52 mtc0 k0, CP0_STATUS 55 li k0, 0xff400000 56 mtc0 k0, $22, 6 62 or k0, k1 64 sw k1, 0(k0) 69 la k0, bmips_reset_nmi_ve [all...] |
H A D | genex.S | 40 PTR_L k0, exception_handlers(k1) 41 jr k0 56 li k0, 31<<2 61 beq k1, k0, handle_vced 62 li k0, 14<<2 63 beq k1, k0, handle_vcei 68 PTR_L k0, exception_handlers(k1) 69 jr k0 78 MFC0 k0, CP0_BADVADDR 80 and k0, k [all...] |
H A D | bmips_5xxx_init.S | 355 la k0, 1f 357 or k0, k1, k0 358 jr k0 381 la k0, 1f 383 or k0, k1, k0 384 xor k0, k1, k0 385 jr k0 [all...] |
/linux-master/arch/mips/dec/prom/ |
H A D | locore.S | 20 mfc0 k0, CP0_STATUS 23 sw k0, 0(k1) 25 mfc0 k0, CP0_EPC 27 addiu k0, 4 # skip the causing instruction 28 jr k0
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/linux-master/arch/sh/boards/mach-hp6xx/ |
H A D | pm_wakeup.S | 11 * k0 scratch 16 #define k0 r0 define 22 and #127, k0 23 mov.b k0, @k1 26 mov.w 6f, k0 27 mov.w k0, @k1
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/linux-master/arch/mips/include/asm/ |
H A D | pm.h | 34 mfc0 k0, CP0_STATUS variable 35 LONG_S k0, PT_STATUS(sp) variable 43 LONG_L k0, PT_STATUS(sp) 44 mtc0 k0, CP0_STATUS variable 75 mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ 76 LONG_S k0, SSS_SEGCTL0(t1) variable 77 mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ variable 78 LONG_S k0, SSS_SEGCTL1(t1) variable 79 mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ variable 80 LONG_S k0, SSS_SEGCTL variable 95 mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ variable 96 LONG_L k0, SSS_SEGCTL1(t1) variable 97 mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ variable 98 LONG_L k0, SSS_SEGCTL2(t1) variable 99 mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ variable [all...] |
H A D | stackframe.h | 112 * k0 and loads the new value in sp. If not, it clobbers k0 and 119 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG 129 LONG_SRL k0, SMP_CPUID_PTRSHIFT variable 130 LONG_ADDU k1, k0 132 move k0, sp 134 .cfi_register sp, k0 156 move k0, ra 165 1: move ra, k0 166 li k0, 199 sll k0, 3 /* extract cu0 bit */ variable 202 move k0, sp variable 229 MTC0 k0, CP0_ENTRYHI variable 277 mfc0 k0, CP0_STATUS variable 278 sll k0, 3 /* extract cu0 bit */ variable 279 bltz k0, 9f variable [all...] |
H A D | regdef.h | 143 #define k0 $26 /* kernel scratch */ macro 186 #define k0 $26 /* kernel temporary */ macro
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/linux-master/drivers/watchdog/ |
H A D | octeon-wdt-nmi.S | 19 dmfc0 k0, $11, 7 21 dins k0, $0, 0, 6 23 ori k0, k0, 0x1c0 | 54 25 dmtc0 k0, $11, 7 30 dmfc0 k0, $31
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/linux-master/arch/sh/kernel/cpu/sh3/ |
H A D | entry.S | 33 * jmp @k0 ! control-transfer instruction 67 #define k0 r0 define 81 * k0 scratch 196 mov.l 2f, k0 197 mov.l @k0, k0 198 jmp @k0 262 mov k3, k0 ! Calculate IMASK-bits 263 shlr2 k0 264 and #0x3c, k0 [all...] |
/linux-master/arch/mips/alchemy/common/ |
H A D | sleeper.S | 45 mfc0 k0, CP0_STATUS 46 sw k0, 0x20(sp) 47 mfc0 k0, CP0_CONTEXT 48 sw k0, 0x1c(sp) 49 mfc0 k0, CP0_PAGEMASK 50 sw k0, 0x18(sp) 51 mfc0 k0, CP0_CONFIG 52 sw k0, 0x14(sp) 67 la k0, alchemy_sleep_wakeup /* resume path */ 68 sw k0, [all...] |
/linux-master/arch/x86/crypto/ |
H A D | nh-sse2-x86_64.S | 34 .macro _nh_stride k0, k1, k2, k3, offset 45 paddd T1, \k0 // reuse k0 to avoid a move 51 pshufd $0x10, \k0, T4 52 pshufd $0x32, \k0, \k0 59 pmuludq T4, \k0 63 paddq \k0, PASS0_SUMS
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/linux-master/arch/arm/crypto/ |
H A D | sha1-ce-core.S | 16 k0 .req q0 68 vld1.32 {k0-k1}, [ip, :128]! 87 vadd.u32 ta0, q8, k0 90 add_update c, 0, k0, 8, 9, 10, 11, dgb 91 add_update c, 1, k0, 9, 10, 11, 8 92 add_update c, 0, k0, 10, 11, 8, 9 93 add_update c, 1, k0, 11, 8, 9, 10
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H A D | sha2-ce-core.S | 16 k0 .req q7 91 vld1.32 {k0}, [rk, :128]! 93 vadd.u32 ta0, q0, k0
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H A D | nh-neon-core.S | 49 .macro _nh_stride k0, k1, k2, k3 58 vadd.u32 T0, T3, \k0
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/linux-master/arch/arm64/crypto/ |
H A D | sha1-ce-core.S | 14 k0 .req v0 70 loadrc k0.4s, 0x5a827999, w6 92 1: add t0.4s, v8.4s, k0.4s 95 add_update c, ev, k0, 8, 9, 10, 11, dgb 96 add_update c, od, k0, 9, 10, 11, 8 97 add_update c, ev, k0, 10, 11, 8, 9 98 add_update c, od, k0, 11, 8, 9, 10
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H A D | nh-neon-core.S | 35 .macro _nh_stride k0, k1, k2, k3 44 add T0.4s, T3.4s, \k0\().4s
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/linux-master/fs/bcachefs/ |
H A D | siphash.c | 88 u64 k0, k1; local 90 k0 = le64_to_cpu(key->k0); 93 ctx->v[0] = 0x736f6d6570736575ULL ^ k0; 95 ctx->v[2] = 0x6c7967656e657261ULL ^ k0;
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H A D | siphash.h | 65 __le64 k0; member in struct:__anon1654
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H A D | str_hash.h | 49 * the siphash_key (k0) is used as the key. 61 .siphash_key = { .k0 = bi->bi_hash_seed } 91 ctx->crc32c = crc32c(~0, &info->siphash_key.k0, 92 sizeof(info->siphash_key.k0)); 95 ctx->crc64 = crc64_be(~0, &info->siphash_key.k0, 96 sizeof(info->siphash_key.k0));
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/linux-master/drivers/soc/bcm/brcmstb/pm/ |
H A D | s3-mips.S | 106 li k0, PM_DEFAULT_MASK 107 mtc0 k0, CP0_PAGEMASK 110 la k0, plat_wired_tlb_setup 111 jalr k0
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/linux-master/crypto/ |
H A D | tea.c | 60 u32 k0, k1, k2, k3; local 68 k0 = ctx->KEY[0]; 77 y += ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1); 88 u32 k0, k1, k2, k3; local 96 k0 = ctx->KEY[0]; 107 y -= ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1);
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