Searched refs:irq_mask (Results 1 - 25 of 644) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-xtensa-pic.c46 u32 irq_mask; local
48 irq_mask = xtensa_get_sr(intenable);
49 irq_mask &= ~BIT(d->hwirq);
50 xtensa_set_sr(irq_mask, intenable);
55 u32 irq_mask; local
57 irq_mask = xtensa_get_sr(intenable);
58 irq_mask |= BIT(d->hwirq);
59 xtensa_set_sr(irq_mask, intenable);
79 .irq_mask = xtensa_irq_mask,
H A Dexynos-combiner.c31 unsigned int irq_mask; member in struct:combiner_chip_data
78 status &= chip_data->irq_mask;
109 .irq_mask = combiner_mask_irq,
129 combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3);
133 writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
231 writel_relaxed(combiner_data[i].irq_mask,
H A Dirq-or1k-pic.c68 .irq_mask = or1k_pic_mask,
78 .irq_mask = or1k_pic_mask,
90 .irq_mask = or1k_pic_mask,
/linux-master/arch/alpha/kernel/
H A Dsys_rx164.c40 volatile unsigned int *irq_mask; local
42 irq_mask = (void *)(POLARIS_DENSE_CONFIG_BASE + 0x74);
43 *irq_mask = mask;
45 *irq_mask;
63 .irq_mask = rx164_disable_irq,
H A Dirq_srm.c41 .irq_mask = srm_disable_irq,
/linux-master/drivers/gpu/drm/tidss/
H A Dtidss_irq.c23 dispc_set_irqenable(tidss->dispc, tidss->irq_mask);
35 tidss->irq_mask |= DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) |
50 tidss->irq_mask &= ~(DSS_IRQ_VP_VSYNC_EVEN(hw_videoport) |
108 tidss->irq_mask = DSS_IRQ_DEVICE_OCP_ERR;
113 tidss->irq_mask |= DSS_IRQ_VP_SYNC_LOST(tcrtc->hw_videoport);
115 tidss->irq_mask |= DSS_IRQ_VP_FRAME_DONE(tcrtc->hw_videoport);
H A Dtidss_drv.h33 dispc_irq_t irq_mask; /* enabled irqs in addition to wait_list */ member in struct:tidss_device
/linux-master/arch/powerpc/include/asm/
H A Dfsl_pm.h25 void (*irq_mask)(int cpu); member in struct:fsl_pm_ops
/linux-master/arch/mips/sgi-ip27/
H A Dip27-irq.c29 u64 *irq_mask[2]; member in struct:hub_irq_data
58 __raw_writeq(mask[0], hd->irq_mask[0]);
59 __raw_writeq(mask[1], hd->irq_mask[1]);
68 __raw_writeq(mask[0], hd->irq_mask[0]);
69 __raw_writeq(mask[1], hd->irq_mask[1]);
84 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_A);
85 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_A);
87 hd->irq_mask[0] = REMOTE_HUB_PTR(nasid, PI_INT_MASK0_B);
88 hd->irq_mask[1] = REMOTE_HUB_PTR(nasid, PI_INT_MASK1_B);
115 .irq_mask
[all...]
/linux-master/arch/mips/loongson2ef/lemote-2f/
H A Dpm.c54 int irq_mask; local
61 irq_mask = inb(PIC_MASTER_IMR);
67 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
/linux-master/drivers/thermal/intel/
H A Dintel_bxt_pmic_thermal.c33 u8 irq_mask; member in struct:trip_config_map
53 .irq_mask = 0x01,
62 .irq_mask = 0x10,
74 .irq_mask = 0x02,
83 .irq_mask = 0x20,
95 .irq_mask = 0x04,
104 .irq_mask = 0x40,
116 .irq_mask = 0x10,
173 mask = td->maps[i].trip_config[j].irq_mask;
/linux-master/include/linux/irqchip/
H A Dchained_irq.h26 chip->irq_mask(&desc->irq_data);
/linux-master/arch/mips/loongson2ef/common/
H A Dbonito-irq.c29 .irq_mask = bonito_irq_disable,
/linux-master/arch/arm/mach-omap2/
H A Ddisplay.c274 u32 v, irq_mask = 0; local
318 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
322 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
324 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
330 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
332 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
338 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
360 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
361 irq_mask) {
/linux-master/drivers/gpu/drm/omapdrm/
H A Domap_irq.c23 u32 irqmask = priv->irq_mask;
92 priv->irq_mask |= framedone_irq;
94 priv->irq_mask &= ~framedone_irq;
123 priv->irq_mask |= dispc_mgr_get_vsync_irq(priv->dispc,
149 priv->irq_mask &= ~dispc_mgr_get_vsync_irq(priv->dispc,
177 irqstatus &= priv->irq_mask & mask;
267 priv->irq_mask = DISPC_IRQ_OCP_ERR;
273 priv->irq_mask |= omap_underflow_irqs[i];
277 priv->irq_mask |= dispc_mgr_get_sync_lost_irq(priv->dispc, i);
/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen2_engine_cs.c297 i915->irq_mask &= ~engine->irq_enable_mask;
298 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
306 i915->irq_mask |= engine->irq_enable_mask;
307 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
312 engine->i915->irq_mask &= ~engine->irq_enable_mask;
313 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
319 engine->i915->irq_mask |= engine->irq_enable_mask;
320 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc-compat.c514 u32 irq_mask; local
525 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
529 irq_mask);
531 DSSERR("failed to register %x isr\n", irq_mask);
542 irq_mask);
544 DSSERR("failed to unregister %x isr\n", irq_mask);
551 u32 irq_mask; local
562 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
565 if (!irq_mask) {
571 irq_mask
[all...]
/linux-master/drivers/clocksource/
H A Dtimer-mediatek-cpux.c51 const unsigned long *irq_mask = cpumask_bits(cpu_possible_mask); local
57 val |= *irq_mask;
59 val &= ~(*irq_mask);
/linux-master/arch/arm/plat-orion/
H A Dirq.c35 ct->chip.irq_mask = irq_gc_mask_clr_bit;
/linux-master/arch/hexagon/kernel/
H A Dirq_cpu.c47 .irq_mask = mask_irq,
/linux-master/kernel/irq/
H A Ddummychip.c60 .irq_mask = noop,
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_interrupts.h65 unsigned long irq_mask; member in struct:dpu_hw_intr
/linux-master/arch/mips/dec/
H A Dioasic-irq.c45 .irq_mask = mask_ioasic_irq,
62 .irq_mask = mask_ioasic_irq,
/linux-master/drivers/i2c/busses/
H A Di2c-cht-wc.c50 u8 irq_mask; member in struct:cht_wc_i2c_adap
72 reg &= ~adap->irq_mask;
233 if (adap->irq_mask != adap->old_irq_mask) {
235 adap->irq_mask);
237 adap->old_irq_mask = adap->irq_mask;
249 adap->irq_mask &= ~CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
256 adap->irq_mask |= CHT_WC_EXTCHGRIRQ_CLIENT_IRQ;
455 adap->old_irq_mask = adap->irq_mask = ~CHT_WC_EXTCHGRIRQ_ADAP_IRQMASK;
461 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ, ~adap->irq_mask);
465 ret = regmap_write(adap->regmap, CHT_WC_EXTCHGRIRQ_MSK, adap->irq_mask);
[all...]
/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_irq.c95 masked_status = status & READ_ONCE(dev_priv->irq_mask);
248 dev_priv->irq_mask |= flag;
249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
259 dev_priv->irq_mask &= ~flag;
260 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);

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