/linux-master/drivers/staging/vt6655/ |
H A D | mac.c | 87 * io_base - Base Address for MAC 100 void __iomem *io_base = priv->port_offset; local 102 return !(ioread8(io_base + reg_offset) & mask); 111 * io_base - Base Address for MAC 121 void __iomem *io_base = priv->port_offset; local 123 iowrite8(retry_limit, io_base + MAC_REG_SRT); 132 * io_base - Base Address for MAC 143 void __iomem *io_base = priv->port_offset; local 145 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); 154 * io_base 164 void __iomem *io_base = priv->port_offset; local 186 void __iomem *io_base = priv->port_offset; local 216 void __iomem *io_base = priv->port_offset; local 267 void __iomem *io_base = priv->port_offset; local 327 void __iomem *io_base = priv->port_offset; local 381 void __iomem *io_base = priv->port_offset; local 437 void __iomem *io_base = priv->port_offset; local 472 void __iomem *io_base = priv->port_offset; local 500 void __iomem *io_base = priv->port_offset; local 532 void __iomem *io_base = priv->port_offset; local 566 void __iomem *io_base = priv->port_offset; local 600 void __iomem *io_base = priv->port_offset; local 635 void __iomem *io_base = priv->port_offset; local 678 void __iomem *io_base = priv->port_offset; local 715 void __iomem *io_base = priv->port_offset; local 725 void __iomem *io_base = priv->port_offset; local 736 void __iomem *io_base = priv->port_offset; local 777 void __iomem *io_base = priv->port_offset; local 842 void __iomem *io_base = priv->port_offset; local [all...] |
/linux-master/drivers/gpu/drm/meson/ |
H A D | meson_viu.c | 86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); 88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); 90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); 92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); 94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); 96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); 98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); 101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); 103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); 106 priv->io_base [all...] |
H A D | meson_vpp.c | 38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); 60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); 63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); 85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); 88 priv->io_base + _REG(VPP_SCALE_COEF)); 95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); 98 priv->io_base + _REG(VIU_MISC_CTRL1)); 100 priv->io_base + _REG(VPP_DOLBY_CTRL)); 102 priv->io_base + _REG(VPP_DUMMY_DATA1)); 104 priv->io_base [all...] |
H A D | meson_venc.c | 1046 priv->io_base + _REG(VENC_VDAC_SETTING)); 1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); 1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); 1057 priv->io_base + _REG(ENCI_CFILT_CTRL)); 1060 priv->io_base + _REG(ENCI_CFILT_CTRL2)); 1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); 1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); 1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); 1071 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); 1073 priv->io_base [all...] |
H A D | meson_crtc.c | 100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); 105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); 109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); 112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); 115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); 136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); 140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); 143 priv->io_base + _REG(VPP_MISC)); 192 priv->io_base + _REG(VPP_MISC)); 246 priv->io_base [all...] |
H A D | meson_rdma.c | 39 priv->io_base + _REG(RDMA_CTRL)); 43 priv->io_base + _REG(RDMA_CTRL)); 68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); 75 priv->io_base + _REG(RDMA_CTRL)); 81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); 113 writel_relaxed(val, priv->io_base + _REG(reg)); 122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); 126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); 132 priv->io_base + _REG(RDMA_ACCESS_AUTO));
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H A D | meson_osd_afbcd.c | 85 priv->io_base + _REG(VIU_SW_RESET)); 86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); 105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); 113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); 133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); 139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); 142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); 144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); 147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); 163 priv->io_base [all...] |
/linux-master/arch/powerpc/platforms/embedded6xx/ |
H A D | flipper-pic.c | 49 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 52 clrbits32(io_base + FLIPPER_IMR, mask); 54 out_be32(io_base + FLIPPER_ICR, mask); 60 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 63 out_be32(io_base + FLIPPER_ICR, 1 << irq); 69 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 71 clrbits32(io_base + FLIPPER_IMR, 1 << irq); 77 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 79 setbits32(io_base + FLIPPER_IMR, 1 << irq); 116 static void __flipper_quiesce(void __iomem *io_base) argument 128 void __iomem *io_base; local 165 void __iomem *io_base = flipper_irq_host->host_data; local 211 void __iomem *io_base = flipper_irq_host->host_data; local 221 void __iomem *io_base; local 234 void __iomem *io_base; local [all...] |
H A D | hlwd-pic.c | 45 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 48 clrbits32(io_base + HW_BROADWAY_IMR, mask); 49 out_be32(io_base + HW_BROADWAY_ICR, mask); 55 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 57 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); 63 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 65 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); 71 void __iomem *io_base = irq_data_get_irq_chip_data(d); local 73 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); 76 clrbits32(io_base 110 void __iomem *io_base = h->host_data; local 149 __hlwd_quiesce(void __iomem *io_base) argument 160 void __iomem *io_base; local 231 void __iomem *io_base = hlwd_irq_host->host_data; local [all...] |
/linux-master/drivers/fpga/ |
H A D | ts73xx-fpga.c | 31 void __iomem *io_base; member in struct:ts73xx_fpga_priv 42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); 44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); 59 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, 65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); 79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); 81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); 84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); 86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); 88 reg = readb(priv->io_base [all...] |
/linux-master/sound/isa/ |
H A D | sscape.c | 133 unsigned io_base; member in struct:soundscape 188 static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg, argument 191 outb(reg, ODIE_ADDR_IO(io_base)); 192 outb(val, ODIE_DATA_IO(io_base)); 205 sscape_write_unsafe(s->io_base, reg, val); 213 static inline unsigned char sscape_read_unsafe(unsigned io_base, argument 216 outb(reg, ODIE_ADDR_IO(io_base)); 217 return inb(ODIE_DATA_IO(io_base)); 223 static inline void set_host_mode_unsafe(unsigned io_base) argument 225 outb(0x0, HOST_CTRL_IO(io_base)); 231 set_midi_mode_unsafe(unsigned io_base) argument 240 host_read_unsafe(unsigned io_base) argument 254 host_read_ctrl_unsafe(unsigned io_base, unsigned timeout) argument 270 host_write_unsafe(unsigned io_base, unsigned char data) argument 285 host_write_ctrl_unsafe(unsigned io_base, unsigned char data, unsigned timeout) argument 323 activate_ad1845_unsafe(unsigned io_base) argument 334 sscape_start_dma_unsafe(unsigned io_base, enum GA_REG reg) argument 346 sscape_wait_dma_unsafe(unsigned io_base, enum GA_REG reg, unsigned timeout) argument [all...] |
/linux-master/drivers/hwspinlock/ |
H A D | u8500_hsem.c | 90 void __iomem *io_base; local 97 io_base = devm_platform_ioremap_resource(pdev, 0); 98 if (IS_ERR(io_base)) 99 return PTR_ERR(io_base); 102 val = readl(io_base + HSEM_CTRL_REG); 103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); 106 writel(0xFFFF, io_base + HSEM_ICRALL); 116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; 126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; local 129 writel(0xFFFF, io_base [all...] |
H A D | omap_hwspinlock.c | 78 void __iomem *io_base; local 83 io_base = devm_platform_ioremap_resource(pdev, 0); 84 if (IS_ERR(io_base)) 85 return PTR_ERR(io_base); 97 i = readl(io_base + SYSSTATUS_OFFSET); 120 bank->lock[i].priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
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/linux-master/drivers/watchdog/ |
H A D | ni903x_wdt.c | 40 u16 io_base; member in struct:ni903x_wdt 58 u8 control = inb(wdt->io_base + NIWD_CONTROL); 60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); 61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); 70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); 71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); 72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); 85 control = inb(wdt->io_base + NIWD_CONTROL); 87 outb(control, wdt->io_base + NIWD_CONTROL); 89 counter2 = inb(wdt->io_base [all...] |
H A D | nic7018_wdt.c | 46 u16 io_base; member in struct:nic7018_wdt 96 wdt->io_base + WDT_PRESET_PRESCALE); 111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); 112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); 114 outb(1, wdt->io_base + WDT_RELOAD_PORT); 116 control = inb(wdt->io_base + WDT_CTRL); 117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); 126 outb(0, wdt->io_base + WDT_CTRL); 127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); 128 outb(0xF0, wdt->io_base [all...] |
H A D | tqmx86_wdt.c | 29 void __iomem *io_base; member in struct:tqmx86_wdt 39 iowrite8(0x81, priv->io_base + TQMX86_WDCS); 52 iowrite8(val, priv->io_base + TQMX86_WDCFG); 86 priv->io_base = devm_ioport_map(dev, res->start, resource_size(res)); 87 if (!priv->io_base)
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/linux-master/sound/soc/spear/ |
H A D | spdif_in.c | 38 void *io_base; member in struct:spdif_in_dev 52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); 53 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); 74 writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK); 79 u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL); 91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); 128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); 130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); 131 writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK); 137 ctrl = readl(host->io_base 207 void __iomem *io_base; local [all...] |
H A D | spdif_out.c | 39 void __iomem *io_base; member in struct:spdif_out_dev 46 writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST); 48 writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET, 49 host->io_base + SPDIF_OUT_SOFT_RST); 54 host->io_base + SPDIF_OUT_CFG); 56 writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR); 57 writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR); 99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); 102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); 165 ctrl = readl(host->io_base [all...] |
/linux-master/drivers/pcmcia/ |
H A D | pd6729.h | 19 unsigned long io_base; /* base io address of the socket */ member in struct:pd6729_socket
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/linux-master/drivers/crypto/hisilicon/sec2/ |
H A D | sec_main.c | 433 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); 441 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); 449 reg = readl_relaxed(qm->io_base + 452 writel_relaxed(reg, qm->io_base + 455 reg = readl_relaxed(qm->io_base + 459 writel_relaxed(reg, qm->io_base + 462 reg = readl_relaxed(qm->io_base + 465 writel_relaxed(reg, qm->io_base + 467 reg = readl_relaxed(qm->io_base + 474 writel_relaxed(reg, qm->io_base [all...] |
/linux-master/drivers/crypto/intel/keembay/ |
H A D | ocs-hcu.c | 173 return readl_poll_timeout(hcu_dev->io_base + OCS_HCU_STATUS, val, 182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); 186 hcu_dev->io_base + OCS_HCU_IER); 192 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR); 196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); 198 writel(HCU_DMA_MSI_UNMASK, hcu_dev->io_base + OCS_HCU_DMA_MSI_MASK); 203 writel(HCU_IRQ_DISABLE, hcu_dev->io_base + OCS_HCU_IER); 204 writel(HCU_DMA_MSI_DISABLE, hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); 270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); 272 data->msg_len_lo = readl(hcu_dev->io_base [all...] |
/linux-master/drivers/input/keyboard/ |
H A D | spear-keyboard.c | 57 void __iomem *io_base; member in struct:spear_kbd 76 sts = readl_relaxed(kbd->io_base + STATUS_REG); 86 val = readl_relaxed(kbd->io_base + DATA_REG) & 97 writel_relaxed(0, kbd->io_base + STATUS_REG); 121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); 122 writel_relaxed(1, kbd->io_base + STATUS_REG); 125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); 127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); 138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); 140 writel_relaxed(val, kbd->io_base [all...] |
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_ttm_stolen_mgr.c | 32 resource_size_t io_base; member in struct:xe_ttm_stolen_mgr 80 mgr->io_base = tile->mem.vram.io_start + mgr->stolen_base; 133 * such flag so the address was the io_base. 138 mgr->io_base = pci_resource_start(pdev, 2) + mgr->stolen_base; 172 if (gscpsmi_base >= mgr->io_base && 173 gscpsmi_base < mgr->io_base + stolen_size) { 176 mgr->io_base + stolen_size - gscpsmi_base); 177 stolen_size = gscpsmi_base - mgr->io_base; 193 mgr->io_base = pci_resource_start(to_pci_dev(xe->drm.dev), 2); 234 if (mgr->io_base [all...] |
/linux-master/drivers/mtd/spi-nor/controllers/ |
H A D | nxp-spifi.c | 56 void __iomem *io_base; member in struct:nxp_spifi 68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, 81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); 82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, 114 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); 115 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, 140 writel(cmd, spifi->io_base + SPIFI_CMD); 143 *buf++ = readb(spifi->io_base + SPIFI_DATA); 164 writel(cmd, spifi->io_base + SPIFI_CMD); 167 writeb(*buf++, spifi->io_base [all...] |
/linux-master/drivers/crypto/hisilicon/hpre/ |
H A D | hpre_main.c | 468 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); 469 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); 477 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); 478 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); 521 qm->io_base + offset + HPRE_CORE_ENB); 522 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); 523 ret = readl_relaxed_poll_timeout(qm->io_base + offset + 548 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); 551 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); 552 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base 1198 void __iomem *io_base; local 1241 void __iomem *io_base; local [all...] |