/macosx-10.10/Heimdal-398.1.2/lib/roken/ |
H A D | gettimeofday.c | 52 ull -= 116444736000000000i64; 53 ull /= 10i64; /* ull is now in microseconds */ 55 tp->tv_usec = (ull % 1000000i64); 56 tp->tv_sec = (ull / 1000000i64);
|
/macosx-10.10/llvmCore-3425.0.34/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 67 /// i64. 69 return CurDAG->getTargetConstant(Imm, MVT::i64); 304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 350 // Don't even go down this path for i64, since different logic will be 508 } else if (LHS.getValueType() == MVT::i64) { 514 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS, 518 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS, 531 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS, 533 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor, 540 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LH [all...] |
H A D | PPCISelLowering.cpp | 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 119 setOperationAction(ISD::SREM, MVT::i64, Expand); 120 setOperationAction(ISD::UREM, MVT::i64, Expand); 125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 162 setOperationAction(ISD::CTPOP, MVT::i64 , Expan [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonVarargsCallingConvention.h | 39 (MVT(MVT::i64).getSizeInBits() / 8))) { 63 if (LocVT == MVT::i64 || 119 if (LocVT == MVT::i64 ||
|
H A D | HexagonISelLowering.cpp | 111 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 150 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 225 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 252 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 598 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 644 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 852 } else if (RegVT == MVT::i64) { 1041 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); 1078 setOperationAction(ISD::SDIV, MVT::i64, Expand); 1080 setOperationAction(ISD::SREM, MVT::i64, Expan [all...] |
H A D | HexagonISelDAGToDAG.cpp | 278 if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) { 319 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; 365 SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64, 387 MVT::i64, SDValue(Result_1, 0)); 433 MVT::i64, MVT::Other, 460 MVT::i64, MVT::Other, 500 if (LoadedVT == MVT::i64) { 523 // For zero ext i64 loads, we need to add combine instructions. 524 if (LD->getValueType(0) == MVT::i64 && 528 if (LD->getValueType(0) == MVT::i64 [all...] |
H A D | HexagonCallingConvLower.cpp | 108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
/macosx-10.10/libarchive-30/libarchive/libarchive/ |
H A D | archive_private.h | 117 # define ARCHIVE_LITERAL_LL(x) x##i64
|
/macosx-10.10/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 108 addRegisterClass(MVT::i64, &SPU::R64CRegClass); 121 setTruncStoreAction(MVT::i128, MVT::i64, Expand); 171 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 196 setOperationAction(ISD::SREM, MVT::i64, Expand); 197 setOperationAction(ISD::UREM, MVT::i64, Expand); 198 setOperationAction(ISD::SDIV, MVT::i64, Expand); 199 setOperationAction(ISD::UDIV, MVT::i64, Expand); 200 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 201 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 247 setOperationAction(ISD::SHL, MVT::i64, Lega [all...] |
H A D | SPUISelDAGToDAG.cpp | 189 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || 190 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || 191 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) { 226 //! Emit the instruction sequence for i64 shl 229 //! Emit the instruction sequence for i64 srl 232 //! Emit the instruction sequence for i64 sra 235 //! Emit the necessary sequence for loading i64 constants: 238 //! Alternate instruction emit sequence for loading i64 constants 584 case MVT::i64: 634 } else if (Opc == ISD::Constant && OpVT == MVT::i64) { [all...] |
/macosx-10.10/libiconv-42/libiconv/srclib/ |
H A D | stdint_.h | 376 # define INT64_MIN (-1i64 << (@BITSIZEOF_INT64_T@ - 1)) 391 # define INT64_MAX (~ (-1i64 << (@BITSIZEOF_INT64_T@ - 1))) 401 # define INT64_MAX 9223372036854775807i64 518 # define INT_LEAST64_MIN (-1i64 << (@BITSIZEOF_INT_LEAST64_T@ - 1)) 533 # define INT_LEAST64_MAX (~ (-1i64 << (@BITSIZEOF_INT_LEAST64_T@ - 1))) 684 # define INT_FAST64_MIN (-1i64 << (@BITSIZEOF_INT_FAST64_T@ - 1)) 699 # define INT_FAST64_MAX (~ (-1i64 << (@BITSIZEOF_INT_FAST64_T@ - 1))) 999 # define INT64_C(x) x##i64 1014 # define INTMAX_C(x) x##i64
|
/macosx-10.10/SmartcardCCID-55008/libusb/libusb/msvc/ |
H A D | stdint.h | 245 #define INT64_C(val) val##i64 253 #define INTMAX_C(val) val##i64
|
/macosx-10.10/dtrace-147/test/tst/common/typedef/ |
H A D | tst.TypedefDataAssign.d | 87 new_int64 i64;
|
/macosx-10.10/ruby-106/ruby/lib/ |
H A D | securerandom.rb | 231 i64 = SecureRandom.random_bytes(8).unpack("Q")[0] 232 Math.ldexp(i64 >> (64-Float::MANT_DIG), -Float::MANT_DIG)
|
/macosx-10.10/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86SelectionDAGInfo.cpp | 105 AVT = MVT::i64; 151 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); 152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : 215 AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
/macosx-10.10/mDNSResponder-561.1.1/mDNSWindows/ |
H A D | PosixCompat.c | 101 #define EPOCHFILETIME (116444736000000000i64)
|
/macosx-10.10/xar-254/xar/lib/ |
H A D | util.c | 59 uint64_t i64; member in union:conv 64 out.i64 = num; 65 return out.i64; 70 return(out.i64);
|
/macosx-10.10/ICU-531.30/icuSources/test/intltest/ |
H A D | winnmtst.cpp | 236 int64_t i64 = randomInt64(); local 242 getWindowsFormat(lcid, currency, w6Buffer, L"%I64d", i64); 260 wnf->format(i64, u6Buffer);
|
/macosx-10.10/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 126 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 205 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 206 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 207 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 208 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 209 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 210 setOperationAction(ISD::SELECT, MVT::i64, Custom); 211 setOperationAction(ISD::LOAD, MVT::i64, Custom); 212 setOperationAction(ISD::STORE, MVT::i64, Custom); 225 setOperationAction(ISD::SDIV, MVT::i64, Expan [all...] |
H A D | MipsISelDAGToDAG.cpp | 490 Mips::ZERO_64, MVT::i64); 519 MVT::i64); 525 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); 528 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, 529 CurDAG->getRegister(Mips::ZERO_64, MVT::i64), 535 MVT::i64); 536 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
|
/macosx-10.10/Libc-1044.1.2/stdtime/FreeBSD/ |
H A D | strptime.c | 560 int64_t i64 = 0; local 564 i64 *= 10; 565 i64 += *buf - '0'; 567 savei = i64; 570 if (i64 > INT_MAX) { 590 if (i64 < 1900) 593 tm->tm_year = i64 - 1900;
|
/macosx-10.10/top-100.1.2/ |
H A D | libtop.c | 1500 pinfo->psamp.faults.i64 = libtop_i64_init(0, pinfo->psamp.events.faults); 1501 pinfo->psamp.pageins.i64 = libtop_i64_init(0, pinfo->psamp.events.pageins); 1502 pinfo->psamp.cow_faults.i64 = libtop_i64_init(0, pinfo->psamp.events.cow_faults); 1503 pinfo->psamp.messages_sent.i64 = libtop_i64_init(0, pinfo->psamp.events.messages_sent); 1504 pinfo->psamp.messages_recv.i64 = libtop_i64_init(0, pinfo->psamp.events.messages_received); 1505 pinfo->psamp.syscalls_mach.i64 = libtop_i64_init(0, pinfo->psamp.events.syscalls_mach); 1506 pinfo->psamp.syscalls_bsd.i64 = libtop_i64_init(0, pinfo->psamp.events.syscalls_unix); 1507 pinfo->psamp.csw.i64 = libtop_i64_init(0, pinfo->psamp.events.csw); 1510 libtop_i64_update(&pinfo->psamp.faults.i64, pinfo->psamp.events.faults); 1511 libtop_i64_update(&pinfo->psamp.pageins.i64, pinf 2574 libtop_i64_t i64; local [all...] |
/macosx-10.10/ICU-531.30/icuSources/test/iotest/ |
H A D | iotest.cpp | 214 int64_t i64; local 278 i64 = uto64(argument); 279 uBufferLenReturned = u_sprintf_u(uBuffer, format, i64); 280 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i64); 379 int64_t i64, expected64; local 469 uBufferLenReturned = u_sscanf_u(argument, format, &i64); 470 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i64); 471 if (i64 != expected64) { 583 int64_t i64; local 634 i64 [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 214 case MVT::i64: Opcode = NVPTX::LD_i64_avar; break; 244 case MVT::i64: Opcode = NVPTX::LD_i64_asi; break; 274 case MVT::i64: Opcode = NVPTX::LD_i64_ari; break; 303 case MVT::i64: Opcode = NVPTX::LD_i64_areg; break; 400 case MVT::i64: Opcode = NVPTX::ST_i64_avar; break; 431 case MVT::i64: Opcode = NVPTX::ST_i64_asi; break; 462 case MVT::i64: Opcode = NVPTX::ST_i64_ari; break; 491 case MVT::i64: Opcode = NVPTX::ST_i64_areg; break; 573 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64); 616 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64); [all...] |
/macosx-10.10/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 260 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 664 if (TLI.isTypeLegal(MVT::i64)) { 666 zextOrTrunc(64), MVT::i64); 1983 case MVT::i64: LC = Call_I64; break; 1998 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2045 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2160 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2163 // Implementation of unsigned i64 to f64 following the algorithm in 2168 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2170 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); [all...] |