Searched refs:hwsp (Results 1 - 9 of 9) sorted by relevance
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_timeline.c | 77 struct i915_vma *hwsp, 85 if (hwsp) { 87 timeline->hwsp_ggtt = i915_vma_get(hwsp); 90 hwsp = hwsp_alloc(gt); 91 if (IS_ERR(hwsp)) 92 return PTR_ERR(hwsp); 93 timeline->hwsp_ggtt = hwsp; 99 GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size); 170 struct i915_vma *hwsp = engine->status_page.vma; local 173 tl = __intel_timeline_create(engine->gt, hwsp, offse 75 intel_timeline_init(struct intel_timeline *timeline, struct intel_gt *gt, struct i915_vma *hwsp, unsigned int offset) argument 339 intel_timeline_read_hwsp(struct i915_request *from, struct i915_request *to, u32 *hwsp) argument [all...] |
H A D | intel_ring_submission.c | 78 i915_reg_t hwsp; local 94 hwsp = RENDER_HWS_PGA_GEN7; 97 hwsp = BLT_HWS_PGA_GEN7; 100 hwsp = BSD_HWS_PGA_GEN7; 103 hwsp = VEBOX_HWS_PGA_GEN7; 107 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); 109 hwsp = RING_HWS_PGA(engine->mmio_base); 112 intel_uncore_write_fw(engine->uncore, hwsp, offset); 113 intel_uncore_posting_read_fw(engine->uncore, hwsp);
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H A D | selftest_timeline.c | 744 /* With wrap should come a new hwsp */ 779 u32 seqno, u32 hwsp, 797 *cs++ = hwsp; 897 bool (*op)(u32 hwsp, u32 seqno)) 1032 u32 hwsp, dummy; local 1085 err = intel_timeline_read_hwsp(rq, watcher[0].rq, &hwsp); 1088 rq->fence.seqno, hwsp, 1099 err = intel_timeline_read_hwsp(rq, watcher[1].rq, &hwsp); 1102 rq->fence.seqno, hwsp, 778 emit_read_hwsp(struct i915_request *rq, u32 seqno, u32 hwsp, u32 *addr) argument 896 check_watcher(struct hwsp_watcher *w, const char *name, bool (*op)(u32 hwsp, u32 seqno)) argument
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H A D | intel_engine.h | 263 unsigned int hwsp,
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H A D | intel_engine_cs.c | 1380 unsigned int hwsp, 1392 ce->timeline = page_pack_bits(NULL, hwsp); 1421 struct i915_vma *hwsp = engine->status_page.vma; local 1423 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp); 1425 mutex_lock(&hwsp->vm->mutex); 1427 mutex_unlock(&hwsp->vm->mutex); 2050 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", 2332 drm_printf(m, "\t\tring->hwsp: 0x%08x\n", 1377 intel_engine_create_pinned_context(struct intel_engine_cs *engine, struct i915_address_space *vm, unsigned int ring_size, unsigned int hwsp, struct lock_class_key *key, const char *name) argument
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/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_hw_engine_types.h | 137 /** @hwsp: hardware status page buffer object */ 138 struct xe_bo *hwsp; member in struct:xe_hw_engine
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H A D | xe_hw_engine.c | 305 xe_bo_ggtt_addr(hwe->hwsp)); 492 hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K, 495 if (IS_ERR(hwe->hwsp)) { 496 err = PTR_ERR(hwe->hwsp); 528 xe_bo_unpin_map_no_vm(hwe->hwsp);
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H A D | xe_execlist.c | 81 xe_bo_ggtt_addr(hwe->hwsp));
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_request.h | 486 const u32 *hwsp = READ_ONCE(rq->hwsp_seqno); local 488 return READ_ONCE(*hwsp);
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