Searched refs:hw_ste_p (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/net/ethernet/mellanox/mlx5/core/steering/
H A Ddr_ste_v1.h10 bool dr_ste_v1_is_miss_addr_set(u8 *hw_ste_p);
11 void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr);
12 u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p);
13 void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask);
14 u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p);
15 void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type);
16 u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p);
17 void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size);
18 void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi);
19 void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u3
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H A Ddr_ste.h150 void (*ste_init)(u8 *hw_ste_p, u16 lu_type,
152 void (*set_next_lu_type)(u8 *hw_ste_p, u16 lu_type);
153 u16 (*get_next_lu_type)(u8 *hw_ste_p);
154 bool (*is_miss_addr_set)(u8 *hw_ste_p);
155 void (*set_miss_addr)(u8 *hw_ste_p, u64 miss_addr);
156 u64 (*get_miss_addr)(u8 *hw_ste_p);
157 void (*set_hit_addr)(u8 *hw_ste_p, u64 icm_addr, u32 ht_size);
158 void (*set_byte_mask)(u8 *hw_ste_p, u16 byte_mask);
159 u16 (*get_byte_mask)(u8 *hw_ste_p);
202 void (*prepare_for_postsend)(u8 *hw_ste_p, u3
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H A Ddr_ste_v1.c266 static void dr_ste_v1_set_entry_type(u8 *hw_ste_p, u8 entry_type) argument
268 MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type);
271 bool dr_ste_v1_is_miss_addr_set(u8 *hw_ste_p) argument
273 u8 entry_type = MLX5_GET(ste_match_bwc_v1, hw_ste_p, entry_format);
281 void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) argument
285 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32, index >> 26);
286 MLX5_SET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index);
289 u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p) argument
292 ((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
293 ((u64)MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_3
298 dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask) argument
303 dr_ste_v1_get_byte_mask(u8 *hw_ste_p) argument
308 dr_ste_v1_set_lu_type(u8 *hw_ste_p, u16 lu_type) argument
314 dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type) argument
320 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p) argument
328 dr_ste_v1_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) argument
333 dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size) argument
341 dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi) argument
351 dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size) argument
377 dr_ste_v1_set_counter_id(u8 *hw_ste_p, u32 ctr_id) argument
382 dr_ste_v1_set_reparse(u8 *hw_ste_p) argument
387 dr_ste_v1_set_encap(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, int size) argument
400 dr_ste_v1_set_insert_hdr(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, u8 anchor, u8 offset, int size) argument
420 dr_ste_v1_set_remove_hdr(u8 *hw_ste_p, u8 *s_action, u8 anchor, u8 offset, int size) argument
435 dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action, u32 vlan_hdr) argument
449 dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num) argument
462 dr_ste_v1_set_encap_l3(u8 *hw_ste_p, u8 *frst_s_action, u8 *scnd_d_action, u32 reformat_id, int size) argument
486 dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action) argument
498 dr_ste_v1_set_accelerated_rewrite_actions(u8 *hw_ste_p, u8 *d_action, u16 num_of_actions, u32 rewrite_pattern, u32 rewrite_args, u8 *action_data) argument
521 dr_ste_v1_set_basic_rewrite_actions(u8 *hw_ste_p, u8 *s_action, u16 num_of_actions, u32 rewrite_index) argument
536 dr_ste_v1_set_rewrite_actions(u8 *hw_ste_p, u8 *action, u16 num_of_actions, u32 rewrite_pattern, u32 rewrite_args, u8 *action_data) argument
579 dr_ste_v1_set_match_range_pkt_len(u8 *hw_ste_p, u32 definer_id, u32 min, u32 max) argument
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H A Ddr_ste_v0.c236 static void dr_ste_v0_set_entry_type(u8 *hw_ste_p, u8 entry_type) argument
238 MLX5_SET(ste_general, hw_ste_p, entry_type, entry_type);
241 static u8 dr_ste_v0_get_entry_type(u8 *hw_ste_p) argument
243 return MLX5_GET(ste_general, hw_ste_p, entry_type);
246 static void dr_ste_v0_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) argument
251 MLX5_SET(ste_rx_steering_mult, hw_ste_p, miss_address_39_32, index >> 26);
252 MLX5_SET(ste_rx_steering_mult, hw_ste_p, miss_address_31_6, index);
255 static u64 dr_ste_v0_get_miss_addr(u8 *hw_ste_p) argument
258 ((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) |
259 ((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_39_3
264 dr_ste_v0_set_byte_mask(u8 *hw_ste_p, u16 byte_mask) argument
269 dr_ste_v0_get_byte_mask(u8 *hw_ste_p) argument
274 dr_ste_v0_set_lu_type(u8 *hw_ste_p, u16 lu_type) argument
279 dr_ste_v0_set_next_lu_type(u8 *hw_ste_p, u16 lu_type) argument
284 dr_ste_v0_get_next_lu_type(u8 *hw_ste_p) argument
289 dr_ste_v0_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) argument
294 dr_ste_v0_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size) argument
302 dr_ste_v0_init_full(u8 *hw_ste_p, u16 lu_type, enum dr_ste_v0_entry_type entry_type, u16 gvmi) argument
317 dr_ste_v0_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi) argument
326 dr_ste_v0_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag) argument
332 dr_ste_v0_set_counter_id(u8 *hw_ste_p, u32 ctr_id) argument
339 dr_ste_v0_set_go_back_bit(u8 *hw_ste_p) argument
344 dr_ste_v0_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_hdr, bool go_back) argument
357 dr_ste_v0_set_tx_encap(void *hw_ste_p, u32 reformat_id, int size, bool encap_l3) argument
367 dr_ste_v0_set_rx_decap(u8 *hw_ste_p) argument
374 dr_ste_v0_set_rx_pop_vlan(u8 *hw_ste_p) argument
380 dr_ste_v0_set_rx_decap_l3(u8 *hw_ste_p, bool vlan) argument
388 dr_ste_v0_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, u32 re_write_index) argument
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H A Ddr_ste.c27 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl) argument
30 struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p;
68 static u8 *dr_ste_get_tag(u8 *hw_ste_p) argument
70 struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p;
75 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask) argument
77 struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)hw_ste_p;
95 u8 *hw_ste_p)
101 return ste_ctx->is_miss_addr_set(hw_ste_p);
105 u8 *hw_ste_p, u64 miss_addr)
107 ste_ctx->set_miss_addr(hw_ste_p, miss_add
94 mlx5dr_ste_is_miss_addr_set(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p) argument
104 mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p, u64 miss_addr) argument
393 mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p, u32 ste_size) argument
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H A Ddr_types.h248 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
249 bool mlx5dr_ste_is_miss_addr_set(struct mlx5dr_ste_ctx *ste_ctx, u8 *hw_ste_p);
257 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
1392 u8 *hw_ste_p, u32 ste_size);

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