Searched refs:gmu_write (Results 1 - 4 of 4) sorted by relevance
/linux-master/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gmu.c | 42 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 66 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 147 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 149 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 156 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 220 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 226 gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); 228 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 231 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 247 gmu_write(gm [all...] |
H A D | a6xx_gmu.h | 109 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) function 127 gmu_write(gmu, reg, val | or);
|
H A D | a6xx_hfi.c | 98 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); 121 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR,
|
H A D | a6xx_gpu.c | 1038 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 1040 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 1042 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 1869 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, 1907 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1911 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 2340 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
|
Completed in 143 milliseconds