Searched refs:gam_regs (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp_cm.c221 struct dcn3_xfer_func_reg gam_regs; local
244 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
245 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
246 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
247 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
248 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
249 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
250 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
251 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
252 gam_regs
320 struct color_matrices_reg gam_regs; local
413 struct color_matrices_reg gam_regs; local
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H A Ddcn30_dwb_cm.c85 struct dcn3_xfer_func_reg gam_regs; local
87 dwb3_get_reg_field_ogam(dwbc30, &gam_regs);
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
96 gam_regs
118 struct dcn3_xfer_func_reg gam_regs; local
308 struct color_matrices_reg gam_regs; local
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H A Ddcn30_mpc.c222 struct dcn3_xfer_func_reg gam_regs; local
224 mpc3_ogam_get_reg_field(mpc, &gam_regs);
226 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]);
227 gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]);
228 gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]);
229 gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
230 gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
231 gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
232 gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]);
233 gam_regs
255 struct dcn3_xfer_func_reg gam_regs; local
1056 struct color_matrices_reg gam_regs; local
1148 struct color_matrices_reg gam_regs; local
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H A Ddcn30_dpp.c99 struct color_matrices_reg gam_regs; local
133 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;
134 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;
135 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;
136 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;
140 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12);
141 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34);
145 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12);
146 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34);
153 &gam_regs);
702 struct dcn3_xfer_func_reg gam_regs; local
730 struct dcn3_xfer_func_reg gam_regs; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c97 struct color_matrices_reg gam_regs; local
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
131 &gam_regs);
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
136 gam_regs
188 struct color_matrices_reg gam_regs; local
258 struct color_matrices_reg gam_regs; local
437 struct xfer_func_reg gam_regs; local
466 struct xfer_func_reg gam_regs; local
500 struct color_matrices_reg gam_regs; local
590 struct xfer_func_reg gam_regs; local
619 struct xfer_func_reg gam_regs; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c326 struct xfer_func_reg gam_regs; local
328 mpc2_ogam_get_reg_field(mpc, &gam_regs);
330 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]);
331 gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]);
332 gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]);
333 gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]);
334 gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]);
335 gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]);
336 gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]);
337 gam_regs
353 struct xfer_func_reg gam_regs; local
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H A Ddcn20_dpp_cm.c167 struct color_matrices_reg gam_regs; local
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;
195 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
196 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
198 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12);
199 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34);
205 &gam_regs);
241 struct color_matrices_reg gam_regs; local
446 struct xfer_func_reg gam_regs; local
474 struct xfer_func_reg gam_regs; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c173 struct dcn3_xfer_func_reg gam_regs; local
175 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs);
177 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]);
178 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]);
179 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]);
180 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]);
181 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]);
182 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]);
183 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]);
184 gam_regs
202 struct dcn3_xfer_func_reg gam_regs; local
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