Searched refs:fuses (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/nvmem/
H A Dapple-efuses.c15 void __iomem *fuses; member in struct:apple_efuses_priv
25 *dst++ = readl_relaxed(priv->fuses + offset);
53 priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
54 if (IS_ERR(priv->fuses))
55 return PTR_ERR(priv->fuses);
/linux-master/drivers/crypto/intel/qat/qat_c62x/
H A Dadf_c62x_hw_data.c30 u32 fuses = self->fuses; local
33 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
42 u32 fuses = self->fuses; local
53 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
H A Dadf_drv.c129 &hw_data->fuses);
172 i = (hw_data->fuses & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0;
/linux-master/drivers/crypto/intel/qat/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c30 u32 fuses = self->fuses; local
33 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
42 u32 fuses = self->fuses; local
53 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;
H A Dadf_drv.c129 &hw_data->fuses);
/linux-master/drivers/crypto/intel/qat/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c31 u32 fuses = self->fuses; local
33 return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
39 u32 fuses = self->fuses; local
41 return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK;
101 int sku = (self->fuses & ADF_DH895XCC_FUSECTL_SKU_MASK)
H A Dadf_drv.c129 &hw_data->fuses);
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen2_hw_data.c216 u32 fuses = hw_data->fuses; local
241 if ((straps | fuses) & ADF_POWERGATE_PKE)
244 if ((straps | fuses) & ADF_POWERGATE_DC)
H A Dadf_accel_devices.h265 u32 fuses; member in struct:adf_hw_device_data
/linux-master/drivers/pmdomain/qcom/
H A Dcpr.c808 const struct cpr_fuse *fuses = drv->cpr_fuses; local
812 for (; fuse < end; fuse++, fuses++) {
813 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data);
850 const struct cpr_fuse *fuses = drv->cpr_fuses; local
871 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
881 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
901 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot);
1078 const struct cpr_fuse *fuses = drv->cpr_fuses; local
1176 quot_offset = fuses[fnum].quotient_offset;
1229 struct cpr_fuse *fuses; local
[all...]
/linux-master/drivers/crypto/intel/qat/qat_420xx/
H A Dadf_drv.c82 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses);
H A Dadf_420xx_hw_data.c99 u32 me_disable = self->fuses;
/linux-master/drivers/crypto/intel/qat/qat_4xxx/
H A Dadf_drv.c84 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses);
H A Dadf_4xxx_hw_data.c102 u32 me_disable = self->fuses;
/linux-master/drivers/nvme/target/
H A Dpassthru.c138 id->fuses = 0;
/linux-master/include/linux/
H A Dnvme.h336 __le16 fuses; member in struct:nvme_id_ctrl

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