Searched refs:flush_mask (Results 1 - 11 of 11) sorted by relevance
/linux-master/drivers/gpu/drm/msm/disp/mdp5/ |
H A D | mdp5_mixer.h | 20 uint32_t flush_mask; /* used to commit LM registers */ member in struct:mdp5_hw_mixer
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H A D | mdp5_ctl.c | 37 /* pending flush_mask bits */ 38 u32 flush_mask; member in struct:mdp5_ctl 473 u32 flush_mask) 478 (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) 487 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, argument 493 DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); 495 ctl_mgr->single_flush_pending_mask |= (*flush_mask); 496 *flush_mask = 0; 500 *flush_mask = ctl_mgr->single_flush_pending_mask; 506 DBG("Single FLUSH mask %x,ID %d", *flush_mask, 472 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask) argument 535 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask, bool start) argument [all...] |
H A D | mdp5_pipe.h | 23 uint32_t flush_mask; /* used to commit pipe registers */ member in struct:mdp5_hw_pipe
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H A D | mdp5_ctl.h | 63 * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask). 70 /* @flush_mask: see CTL flush masks definitions below */ 72 u32 flush_mask, bool start);
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H A D | mdp5_crtc.c | 91 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) argument 100 DBG("%s: flush=%08x", crtc->name, flush_mask); 102 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); 115 uint32_t flush_mask = 0; local 124 flush_mask |= mdp5_plane_get_flush(plane); 128 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); 132 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); 134 return crtc_flush(crtc, flush_mask); 962 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); local 1025 crtc_flush(crtc, flush_mask); 1042 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); local [all...] |
H A D | mdp5_mixer.c | 161 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id);
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H A D | mdp5_pipe.c | 168 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe);
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H A D | mdp5_plane.c | 1002 mask = pstate->hwpipe->flush_mask; 1005 mask |= pstate->r_hwpipe->flush_mask;
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/linux-master/drivers/net/wireless/mediatek/mt76/mt7603/ |
H A D | mac.c | 183 u32 flush_mask; local 199 flush_mask = MT_WF_ARB_TX_FLUSH_AC0 | 203 flush_mask <<= mac_idx; 205 mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask); 206 mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000); 207 mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask);
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/linux-master/drivers/infiniband/hw/irdma/ |
H A D | hw.c | 2717 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) argument 2723 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) 2727 info.sq = flush_mask & IRDMA_FLUSH_SQ; 2728 info.rq = flush_mask & IRDMA_FLUSH_RQ; 2737 if (flush_mask & IRDMA_REFLUSH) { 2757 flush_mask & IRDMA_FLUSH_WAIT);
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H A D | main.h | 475 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask);
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