Searched refs:fclk (Results 1 - 25 of 50) sorted by relevance

12

/linux-master/drivers/media/dvb-frontends/
H A Dmb86a20s.h16 * @fclk: Clock frequency. If zero, assumes the default
22 u32 fclk; member in struct:mb86a20s_config
H A Ds5h1420.c39 u32 fclk; member in struct:s5h1420_state
368 tmp = state->fclk / tmp;
475 do_div(val, (state->fclk / 1000));
501 * divide fclk by 1000000 to get the correct value. */
502 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
529 * divide fclk by 1000000 to get the correct value. */
530 val = (((-val) * (state->fclk/1000000)) / (1<<24));
666 /* set s5h1420 fclk PLL according to desired symbol rate */
668 state->fclk = 80000000;
670 state->fclk
[all...]
H A Dcx24110.c231 u32 tmp, fclk, BDRI; local
251 fclk=90999000UL/2;
255 fclk=60666000UL;
259 fclk=80888000UL;
263 fclk=90999000UL;
265 dprintk("cx24110 debug: fclk %d Hz\n",fclk);
275 BDRI=fclk>>2;
288 dprintk("fclk = %d\n", fclk);
[all...]
/linux-master/drivers/usb/host/
H A Dehci-sh.c13 struct clk *iclk, *fclk; member in struct:ehci_sh_priv
114 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck");
115 if (IS_ERR(priv->fclk))
116 priv->fclk = NULL;
122 clk_enable(priv->fclk);
139 clk_disable(priv->fclk);
157 clk_disable(priv->fclk);
H A Dohci-at91.c54 struct clk *fclk; member in struct:ohci_at91_priv
78 clk_set_rate(ohci_at91->fclk, 48000000);
81 clk_prepare_enable(ohci_at91->fclk);
90 clk_disable_unprepare(ohci_at91->fclk);
215 ohci_at91->fclk = devm_clk_get(dev, "uhpck");
216 if (IS_ERR(ohci_at91->fclk)) {
218 retval = PTR_ERR(ohci_at91->fclk);
/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c146 unsigned long tmp, fout, fclk, diff; local
153 fclk = div_u64(parent_rate * n, m);
156 fclk = div_u64(fclk, 100);
158 if (fclk < PLL_FCLK_MIN_FREQ ||
159 fclk > PLL_FCLK_MAX_FREQ)
162 fout = div_u64(fclk, p);
/linux-master/arch/sh/drivers/pci/
H A Dpcie-sh7786.c26 struct clk *fclk, phy_clk; member in struct:sh7786_pcie_port
224 port->fclk = clk_get(NULL, fclk_name);
225 if (IS_ERR(port->fclk)) {
226 ret = PTR_ERR(port->fclk);
230 clk_enable(port->fclk);
250 clk_disable(port->fclk);
251 clk_put(port->fclk);
/linux-master/drivers/pwm/
H A Dpwm-omap-dmtimer.c154 struct clk *fclk; local
163 fclk = omap->pdata->get_fclk(omap->dm_timer);
164 if (!fclk) {
165 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n");
169 clk_rate = clk_get_rate(fclk);
171 dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n");
/linux-master/drivers/clocksource/
H A Dtimer-ti-dm.c122 struct clk *fclk; member in struct:dmtimer
418 if (unlikely(!timer) || IS_ERR(timer->fclk))
447 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
457 ret = clk_set_parent(timer->fclk, parent);
729 if (timer && !IS_ERR(timer->fclk))
730 return timer->fclk;
1136 timer->fclk = devm_clk_get(dev, "fck");
1137 if (IS_ERR(timer->fclk))
1138 return PTR_ERR(timer->fclk);
1141 ret = devm_clk_notifier_register(dev, timer->fclk,
[all...]
/linux-master/drivers/iio/adc/
H A Dad7124.c262 unsigned int fclk, odr_sel_bits; local
264 fclk = clk_get_rate(st->mclk);
272 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
282 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
891 unsigned int fclk, power_mode; local
894 fclk = clk_get_rate(st->mclk);
895 if (!fclk)
901 fclk);
902 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
903 ret = clk_set_rate(st->mclk, fclk);
[all...]
H A Dad7192.c187 u32 fclk; member in struct:ad7192_state
575 return DIV_ROUND_CLOSEST(st->fclk,
583 return DIV_ROUND_CLOSEST(st->fclk,
818 div = st->fclk / (val * ad7192_get_f_order(st) * 1024);
1137 st->fclk = AD7192_INT_FREQ_MHZ;
1147 st->fclk = clk_get_rate(st->mclk);
1148 if (!ad7192_valid_external_frequency(st->fclk)) {
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h32 uint32_t fclk; member in struct:__anon155
H A Dvg_clk_mgr.c399 /* We will not select WM based on fclk, so leave it as unconstrained */
574 if (clock_table->DfPstateTable[i].fclk != 0) {
589 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
594 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 }
/linux-master/drivers/usb/gadget/udc/
H A Dat91_udc.h136 struct clk *iclk, *fclk; member in struct:at91_udc
H A Dat91_udc.c905 clk_enable(udc->fclk);
914 clk_disable(udc->fclk);
1848 udc->fclk = devm_clk_get(dev, "hclk");
1849 if (IS_ERR(udc->fclk))
1850 return PTR_ERR(udc->fclk);
1853 clk_set_rate(udc->fclk, 48000000);
1854 retval = clk_prepare(udc->fclk);
1920 clk_unprepare(udc->fclk);
1947 clk_unprepare(udc->fclk);
/linux-master/sound/soc/ti/
H A Domap-dmic.c36 struct clk *fclk; member in struct:omap_dmic
320 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
330 mux = clk_get_parent(dmic->fclk);
476 dmic->fclk = devm_clk_get(dmic->dev, "fck");
477 if (IS_ERR(dmic->fclk)) {
/linux-master/drivers/i2c/busses/
H A Di2c-omap.c355 struct clk *fclk; local
374 fclk = clk_get(omap->dev, "fck");
375 if (IS_ERR(fclk)) {
376 error = PTR_ERR(fclk);
382 fclk_rate = clk_get_rate(fclk);
383 clk_put(fclk);
404 * The filter is iclk (fclk for HS) period.
413 fclk = clk_get(omap->dev, "fck");
414 if (IS_ERR(fclk)) {
415 error = PTR_ERR(fclk);
[all...]
/linux-master/drivers/clk/zynq/
H A Dclkc.c103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, argument
147 clks[fclk] = clk_register_gate(NULL, clk_name,
152 if (clk_prepare_enable(clks[fclk]))
154 fclk - fclk0);
171 clks[fclk] = ERR_PTR(-ENOMEM);
247 of_property_read_u32(np, "fclk-enable", &fclk_enable);
/linux-master/drivers/net/hamradio/
H A Dbaycom_epp.c167 unsigned int fclk; member in struct:baycom_state::__anon676
304 sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat",
306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
983 if ((cp = strstr(modestr,"fclk="))) {
984 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
985 if (bc->cfg.fclk < 1000000)
986 bc->cfg.fclk = 1000000;
987 if (bc->cfg.fclk > 25000000)
988 bc->cfg.fclk
[all...]
/linux-master/arch/arm/mach-omap2/
H A Dprm3xxx.c230 u32 wkst, fclk, iclk, clken; local
243 fclk = omap2_cm_read_mod_reg(module, fclk_off);
260 omap2_cm_write_mod_reg(fclk, module, fclk_off);
/linux-master/drivers/mmc/host/
H A Domap.c130 struct clk * fclk; member in struct:mmc_omap_host
193 clk_enable(host->fclk);
195 clk_disable(host->fclk);
1157 int func_clk_rate = clk_get_rate(host->fclk);
1429 host->fclk = clk_get(&pdev->dev, "fck");
1430 if (IS_ERR(host->fclk)) {
1431 ret = PTR_ERR(host->fclk);
1435 ret = clk_prepare(host->fclk);
1509 clk_unprepare(host->fclk);
1511 clk_put(host->fclk);
[all...]
H A Domap_hsmmc.c175 struct clk *fclk; member in struct:omap_hsmmc_host
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
1432 host->clk_rate = clk_get_rate(host->fclk);
1841 host->fclk = devm_clk_get(&pdev->dev, "fck");
1842 if (IS_ERR(host->fclk)) {
1843 ret = PTR_ERR(host->fclk);
1844 host->fclk = NULL;
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h114 uint32_t fclk; member in struct:__anon510
/linux-master/drivers/clk/samsung/
H A Dclk-exynos4.c1042 struct samsung_fixed_rate_clock fclk; local
1058 fclk.id = CLK_FIN_PLL;
1059 fclk.name = "fin_pll";
1060 fclk.parent_name = NULL;
1061 fclk.flags = 0;
1062 fclk.fixed_rate = finpll_f;
1063 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
/linux-master/drivers/spi/
H A Dspi-ti-qspi.c49 struct clk *fclk; member in struct:ti_qspi
177 clk_rate = clk_get_rate(qspi->fclk);
845 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
846 if (IS_ERR(qspi->fclk)) {
847 ret = PTR_ERR(qspi->fclk);

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