Searched refs:ed_asic_outb (Results 1 - 8 of 8) sorted by path
| /freebsd-11-stable/sys/dev/ed/ |
| H A D | if_ed_3c503.c | 163 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
175 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
201 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
211 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
302 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
303 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
315 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
318 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
321 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
324 ed_asic_outb(s
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| H A D | if_ed_cbus.c | 693 ed_asic_outb(sc, ED_NOVELL_RESET, (tmp & 0xf0) | 0x08);
696 ed_asic_outb(sc, 0x08, tmp);
697 ed_asic_outb(sc, 0x08, tmp & 0x7f);
701 ed_asic_outb(sc, ED_NOVELL_RESET, 0x00);
703 ed_asic_outb(sc, ED_NOVELL_RESET, 0x01);
717 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
826 ed_asic_outb(sc, 0, 0x00);
830 ed_asic_outb(sc, 0, 0x94);
832 ed_asic_outb(sc, 0, 0x94);
835 ed_asic_outb(s
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| H A D | if_ed_novell.c | 79 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
89 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
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| H A D | if_ed_pccard.c | 729 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2);
731 ed_asic_outb(sc, ED_DL100XX_MIIBUS,
734 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2);
736 ed_asic_outb(sc, ED_DL100XX_MIIBUS,
739 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 0);
749 ed_asic_outb(sc, ED_DL100XX_MIIBUS, val);
779 ed_asic_outb(sc, ED_NOVELL_RESET, ed_asic_inb(sc, ED_NOVELL_RESET));
967 ed_asic_outb(sc, ED_AX88X90_MIIBUS, val);
1086 ed_asic_outb(sc, ED_AX88X90_GPIO,
1089 ed_asic_outb(s
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| H A D | if_ed_sic.c | 97 ed_asic_outb(sc, 0, 0x00);
105 ed_asic_outb(sc, 0, 0x81);
129 ed_asic_outb(sc, 0, 0x80);
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| H A D | if_ed_wd80x3.c | 106 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
133 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
135 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
138 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
203 ed_asic_outb(sc, ED_WD790_HWR,
224 ed_asic_outb(sc, ED_WD790_HWR,
312 ed_asic_outb(sc, ED_WD_IRR,
316 ed_asic_outb(sc, ED_WD790_HWR,
321 ed_asic_outb(sc, ED_WD790_HWR,
337 ed_asic_outb(s
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| H A D | if_edvar.h | 164 #define ed_asic_outb(sc, port, value) \ macro
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| H A D | if_ed.c | 141 ed_asic_outb(sc, ED_WD_MSR, 0x00);
142 ed_asic_outb(sc, ED_WD_LAAR,
151 ed_asic_outb(sc, ED_WD_LAAR,
154 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
1765 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL);
1775 ed_asic_outb(sc, ED_WD_LAAR,
1778 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
1809 ed_asic_outb(sc, ED_3COM_GACFR,
1816 ed_asic_outb(sc, ED_WD_MSR, 0x00);
1817 ed_asic_outb(s
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Completed in 139 milliseconds