Searched refs:dsaf_set_dev_bit (Results 1 - 6 of 6) sorted by last modified time

/linux-master/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_xgmac.c93 dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_TX_B, !!value);
103 dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_RX_B, !!value);
278 dsaf_set_dev_bit(drv, XGMAC_MAC_PAUSE_CTRL_REG,
H A Dhns_dsaf_gmac.c67 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
71 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0);
72 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
82 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
86 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1);
87 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
159 dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
261 dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
294 dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG,
296 dsaf_set_dev_bit(dr
[all...]
H A Dhns_dsaf_main.c214 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
225 dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
357 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
362 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
765 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
792 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
1182 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1184 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1198 dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
H A Dhns_dsaf_rcb.c402 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
404 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
406 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,
H A Dhns_dsaf_ppe.c17 dsaf_set_dev_bit(ppe_cb, PPEV2_CFG_TSO_EN_REG, 0, !!value);
132 dsaf_set_dev_bit(ppe_cb, PPE_TNL_0_5_CNT_CLR_CE_REG,
247 dsaf_set_dev_bit(ppe_common, PPE_COM_COMMON_CNT_CLR_CE_REG,
H A Dhns_dsaf_reg.h1064 #define dsaf_set_dev_bit(dev, reg, bit, val) \ macro

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