Searched refs:divider (Results 1 - 25 of 147) sorted by relevance

123456

/linux-master/drivers/clk/qcom/
H A Dclk-regmap-divider.c11 #include "clk-regmap-divider.h"
21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
22 struct clk_regmap *clkr = &divider->clkr;
25 regmap_read(clkr->regmap, divider->reg, &val);
26 val >>= divider->shift;
27 val &= BIT(divider->width) - 1;
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width,
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width,
45 struct clk_regmap_div *divider local
60 struct clk_regmap_div *divider = to_clk_regmap_div(hw); local
[all...]
/linux-master/drivers/clk/tegra/
H A Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, argument
26 div = div_frac_get(rate, parent_rate, divider->width,
27 divider->frac_width, divider->flags);
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); local
43 reg = readl_relaxed(divider->reg);
45 if ((divider->flags & TEGRA_DIVIDER_UART) &&
49 div = (reg >> divider->shift) & div_mask(divider);
51 mul = get_mul(divider);
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); local
83 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); local
139 struct tegra_clk_frac_div *divider; local
[all...]
/linux-master/drivers/clk/ti/
H A Ddivider.c32 static void _setup_mask(struct clk_omap_divider *divider) argument
38 if (divider->table) {
41 for (clkt = divider->table; clkt->div; clkt++)
45 max_val = divider->max;
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) &&
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO))
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
57 divider->mask = (1 << fls(mask)) - 1;
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) argument
62 if (divider
82 _get_val(struct clk_omap_divider *divider, u8 div) argument
96 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local
130 _is_valid_div(struct clk_omap_divider *divider, unsigned int div) argument
171 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local
238 struct clk_omap_divider *divider; local
274 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local
291 struct clk_omap_divider *divider = to_clk_omap_divider(hw); local
331 ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, u8 flags, struct clk_omap_divider *divider) argument
434 _populate_divider_min_max(struct device_node *node, struct clk_omap_divider *divider) argument
[all...]
H A Dclk-dra7-atl.c49 u32 divider; /* Cached divider value */ member in struct:dra7_atl_desc
85 cdesc->divider - 1);
120 return parent_rate / cdesc->divider;
126 unsigned divider; local
128 divider = (*parent_rate + rate / 2) / rate;
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1)
130 divider = DRA7_ATL_DIVIDER_MASK + 1;
132 return *parent_rate / divider;
139 u32 divider; local
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-fixup-div.c15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member in struct:clk_fixup_div
31 struct clk_divider *divider = to_clk_divider(hw); local
33 return container_of(divider, struct clk_fixup_div, divider);
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
57 unsigned int divider, valu local
[all...]
H A Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); local
36 prediv_value = readl(divider->reg) >> divider->shift;
37 prediv_value &= clk_div_mask(divider->width);
40 NULL, divider->flags,
41 divider->width);
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
47 divider->flags, PCG_DIV_WIDTH);
95 struct clk_divider *divider = to_clk_divider(hw); local
107 spin_lock_irqsave(divider
127 struct clk_divider *divider = to_clk_divider(hw); local
[all...]
H A Dclk-composite-93.c109 struct clk_divider *divider = to_clk_divider(hw); local
115 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags);
119 if (divider->lock)
120 spin_lock_irqsave(divider->lock, flags);
122 val = readl(divider->reg);
123 val &= ~(clk_div_mask(divider->width) << divider->shift);
124 val |= (u32)value << divider
[all...]
H A Dclk-divider-gate.c15 struct clk_divider divider; member in struct:clk_divider_gate
23 return container_of(div, struct clk_divider_gate, divider);
170 * NOTE: In order to reuse the most code from the common divider,
171 * we also design our divider following the way that provids an extra
201 div_gate->divider.reg = reg;
202 div_gate->divider.shift = shift;
203 div_gate->divider.width = width;
204 div_gate->divider.lock = lock;
205 div_gate->divider.table = table;
206 div_gate->divider
[all...]
/linux-master/drivers/clk/zynqmp/
H A DMakefile4 obj-$(CONFIG_ARCH_ZYNQMP) += pll.o clk-gate-zynqmp.o divider.o clk-mux-zynqmp.o clkc.o
H A Ddivider.c7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
84 u32 clk_id = divider->clk_id;
85 u32 div_type = divider->div_type;
92 pr_debug("%s() get divider faile
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
172 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); local
[all...]
/linux-master/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member in struct:clk_div
30 struct clk_divider *divider = to_clk_divider(hw); local
32 return container_of(divider, struct clk_div, divider);
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate);
48 return div->ops->round_rate(&div->divider.hw, rate, prate);
57 ret = div->ops->set_rate(&div->divider
[all...]
/linux-master/drivers/clk/mvebu/
H A Ddove-divider.c3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; local
59 divider = val & ~(~0 << dc->div_bit_size);
62 divider = dc->divider_table[divider];
64 return divider;
70 unsigned int divider, max; local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate);
78 if (divider
102 unsigned int divider = dove_get_divider(dc); local
116 int divider; local
135 int divider; local
[all...]
/linux-master/include/linux/
H A Dpolynomial.h13 * @divider: distributed divider per each degree.
14 * @divider_leftover: divider leftover, which couldn't be redistributed.
19 long divider; member in struct:polynomial_term
25 * @total_divider: total data divider.
/linux-master/drivers/clk/nuvoton/
H A DMakefile3 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o
/linux-master/drivers/clk/rockchip/
H A Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); local
28 val = readl(divider->reg) >> divider->shift;
29 val &= div_mask(divider->width);
60 * The maximum divider we can use without overflowing
70 * parent rate, so return the divider immediately.
98 struct clk_divider *divider = to_clk_divider(hw); local
102 divider->width,
103 divider->flags);
111 struct clk_divider *divider local
[all...]
/linux-master/drivers/clk/
H A Dclk-divider.c7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
32 return ioread32be(divider->reg);
34 return readl(divider->reg);
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
40 iowrite32be(val, divider->reg);
42 writel(val, divider
152 struct clk_divider *divider = to_clk_divider(hw); local
431 struct clk_divider *divider = to_clk_divider(hw); local
452 struct clk_divider *divider = to_clk_divider(hw); local
490 struct clk_divider *divider = to_clk_divider(hw); local
[all...]
H A Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); local
382 val = readl(divider->reg) >> divider->shift;
383 val &= clk_div_mask(divider->width);
385 return divider_recalc_rate(hw, parent_rate, val, divider->table,
386 divider->flags, divider->width);
392 struct m10v_clk_divider *divider = to_m10v_div(hw); local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
398 val = readl(divider
413 struct m10v_clk_divider *divider = to_m10v_div(hw); local
[all...]
/linux-master/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c111 /* Extract divider instance from clock hardware instance */
147 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150 * @base: base address of register containing the divider
151 * @offset: offset address of register containing the divider
152 * @shift: shift to the divider bit field
153 * @width: width of the divider bit field
154 * @flags: clk_wzrd divider flags
155 * @table: array of value/divider pairs, last entry should have div = 0
157 * @d: value of the common divider
158 * @o: value of the leaf divider
194 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
219 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
233 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
281 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
337 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
375 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
410 clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr) argument
434 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
499 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
535 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
551 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
567 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
585 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
651 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
704 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
720 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); local
[all...]
/linux-master/drivers/clk/stm32/
H A Dclk-stm32-core.c213 const struct stm32_div_cfg *divider = &data->dividers[div_id]; local
217 val = readl(base + divider->offset) >> divider->shift;
218 val &= clk_div_mask(divider->width);
219 div = _get_div(divider->table, val, divider->flags, divider->width);
222 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
236 const struct stm32_div_cfg *divider = &data->dividers[div_id]; local
240 value = divider_get_val(rate, parent_rate, divider
359 const struct stm32_div_cfg *divider; local
436 const struct stm32_div_cfg *divider; local
[all...]
/linux-master/include/media/i2c/
H A Dmt9t112.h19 * @divider: Sensor PLL configuration
24 struct mt9t112_pll_divider divider; member in struct:mt9t112_platform_data
/linux-master/drivers/clk/baikal-t1/
H A Dccu-div.c78 unsigned long divider)
85 nd = ccu_div_lock_delay_ns(parent_rate, divider);
211 unsigned long divider; local
215 divider = ccu_div_get(div->mask, val);
217 return ccu_div_calc_freq(parent_rate, divider);
224 unsigned long divider; local
226 divider = parent_rate / rate;
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
235 unsigned long divider; local
237 divider
76 ccu_div_var_update_clkdiv(struct ccu_div *div, unsigned long parent_rate, unsigned long divider) argument
251 unsigned long flags, divider; local
285 unsigned long flags, divider; local
[all...]
/linux-master/drivers/clk/meson/
H A Dvid-pll-div.c20 * This vid_pll divided is a fully programmable fractionnal divider to
29 unsigned int divider; member in struct:vid_pll_div
37 .divider = (_ft), \
84 if (!div || !div->divider) {
89 return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
97 MODULE_DESCRIPTION("Amlogic video pll divider driver");
/linux-master/arch/x86/kernel/
H A Dtsc_msr.c40 u32 divider; member in struct:muldiv
197 if (md->divider) {
199 freq = DIV_ROUND_CLOSEST(tscref, md->divider);
204 res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.h46 uint32_t dentist_get_did_from_divider(int divider);
/linux-master/lib/
H A Dpolynomial.c91 * divider (as for the rationale fraction representation), data
92 * power and the rational fraction divider leftover. Then all of
94 * normalized by the total divider before being returned.
99 tmp = mult_frac(tmp, data, term->divider);

Completed in 343 milliseconds

123456