Searched refs:div_hw (Results 1 - 14 of 14) sorted by relevance

/linux-master/drivers/clk/actions/
H A Dowl-divider.c17 const struct owl_divider_hw *div_hw,
22 div_hw->table, div_hw->width,
23 div_hw->div_flags);
31 return owl_divider_helper_round_rate(&div->common, &div->div_hw,
36 const struct owl_divider_hw *div_hw,
42 regmap_read(common->regmap, div_hw->reg, &reg);
43 val = reg >> div_hw->shift;
44 val &= (1 << div_hw->width) - 1;
47 val, div_hw
16 owl_divider_helper_round_rate(struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long rate, unsigned long *parent_rate) argument
35 owl_divider_helper_recalc_rate(struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long parent_rate) argument
61 owl_divider_helper_set_rate(const struct owl_clk_common *common, const struct owl_divider_hw *div_hw, unsigned long rate, unsigned long parent_rate) argument
[all...]
H A Dowl-divider.h25 struct owl_divider_hw div_hw; member in struct:owl_divider
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
60 const struct owl_divider_hw *div_hw,
65 const struct owl_divider_hw *div_hw,
69 const struct owl_divider_hw *div_hw,
H A Dowl-composite.h22 struct owl_divider_hw div_hw; member in union:owl_rate
42 .rate.div_hw = _div, \
56 .rate.div_hw = _div, \
H A Dowl-composite.c62 rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
76 return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw,
85 return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw,
/linux-master/drivers/clk/tegra/
H A Dclk-periph.c41 struct clk_hw *div_hw = &periph->divider.hw; local
43 __clk_hw_set_clk(div_hw, hw);
45 return div_ops->recalc_rate(div_hw, parent_rate);
53 struct clk_hw *div_hw = &periph->divider.hw; local
56 __clk_hw_set_clk(div_hw, hw);
58 rate = div_ops->round_rate(div_hw, req->rate, &req->best_parent_rate);
71 struct clk_hw *div_hw = &periph->divider.hw; local
73 __clk_hw_set_clk(div_hw, hw);
75 return div_ops->set_rate(div_hw, rate, parent_rate);
122 struct clk_hw *div_hw local
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H A Dclk-super.c149 struct clk_hw *div_hw = &super->frac_div.hw; local
152 __clk_hw_set_clk(div_hw, hw);
154 rate = super->div_ops->round_rate(div_hw, req->rate,
167 struct clk_hw *div_hw = &super->frac_div.hw; local
169 __clk_hw_set_clk(div_hw, hw);
171 return super->div_ops->recalc_rate(div_hw, parent_rate);
178 struct clk_hw *div_hw = &super->frac_div.hw; local
180 __clk_hw_set_clk(div_hw, hw);
182 return super->div_ops->set_rate(div_hw, rate, parent_rate);
188 struct clk_hw *div_hw local
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/linux-master/drivers/clk/imx/
H A Dclk-composite-93.c189 struct clk_hw *div_hw, *gate_hw; local
210 div_hw = &div->hw;
223 mux_hw, &clk_mux_ro_ops, div_hw,
237 mux_hw, &imx93_clk_composite_mux_ops, div_hw,
243 mux_hw, &imx93_clk_composite_mux_ops, div_hw,
H A Dclk-composite-8m.c214 struct clk_hw *div_hw, *gate_hw = NULL; local
235 div_hw = &div->hw;
272 mux_hw, mux_ops, div_hw,
/linux-master/drivers/clk/
H A Dclk-bm1880.c592 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); local
593 struct bm1880_div_clock *div = &div_hw->div;
594 void __iomem *reg_addr = div_hw->base + div->reg;
614 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); local
615 struct bm1880_div_clock *div = &div_hw->div;
616 void __iomem *reg_addr = div_hw->base + div->reg;
636 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); local
637 struct bm1880_div_clock *div = &div_hw->div;
638 void __iomem *reg_addr = div_hw->base + div->reg;
644 div->width, div_hw
761 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; local
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H A Dclk-stm32h7.c351 struct clk_hw *div_hw; member in struct:composite_cfg
368 struct clk_hw *div_hw; local
372 mux_hw = div_hw = gate_hw = NULL;
394 div_hw = &div->hw;
415 composite->div_hw = div_hw;
1326 c_cfg.div_hw, c_cfg.div_ops,
1349 c_cfg.div_hw, c_cfg.div_ops,
1364 c_cfg.div_hw, c_cfg.div_ops,
1378 c_cfg.div_hw, c_cf
[all...]
/linux-master/drivers/clk/nxp/
H A Dclk-lpc18xx-ccu.c208 struct clk_hw *div_hw = NULL; local
220 div_hw = &div->hw;
229 div_hw, div_ops,
H A Dclk-lpc32xx.c1434 struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; local
1447 div_hw = &div0->clk.hw;
1456 mux_hw, mops, div_hw, dops,
/linux-master/drivers/clk/mediatek/
H A Dclk-mtk.c225 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; local
281 div_hw = &div->hw;
287 div_hw, div_ops,
/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp1.c633 struct clk_hw *mux_hw, *div_hw, *gate_hw; local
636 div_hw = NULL;
654 div_hw = _get_stm32_div(dev, base, cfg->div, lock);
656 if (!IS_ERR(div_hw)) {
676 mux_hw, mux_ops, div_hw, div_ops,

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