Searched refs:disp_int (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Drs600.c726 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
727 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
731 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
735 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
740 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
746 rdev->irq.stat_regs.r500.disp_int = 0;
786 !rdev->irq.stat_regs.r500.disp_int &&
791 rdev->irq.stat_regs.r500.disp_int ||
798 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
807 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
[all...]
H A Dr600.c3916 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3927 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3940 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3942 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3946 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3948 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3959 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4134 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT))
4144 rdev->irq.stat_regs.r600.disp_int
[all...]
H A Dsi.c6128 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local
6135 disp_int[i] = RREG32(si_disp_int_status[i]);
6149 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
6152 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
6159 if (disp_int[i] & DC_HPD1_INTERRUPT)
6164 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
6227 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local
6298 if (!(disp_int[crtc_id
[all...]
H A Devergreen.c4615 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local
4619 disp_int[i] = RREG32(evergreen_disp_int_status[i]);
4634 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
4637 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
4644 if (disp_int[i] & DC_HPD1_INTERRUPT)
4649 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
4702 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local
4774 if (!(disp_int[crtc_id
[all...]
H A Dcik.c7289 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7320 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7322 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7363 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7393 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
7584 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
7594 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7599 if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
7602 rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7774 if (!(rdev->irq.stat_regs.cik.disp_int
[all...]
H A Dradeon.h709 u32 disp_int; member in struct:r500_irq_stat_regs
714 u32 disp_int; member in struct:r600_irq_stat_regs
724 u32 disp_int[6]; member in struct:evergreen_irq_stat_regs
730 u32 disp_int; member in struct:cik_irq_stat_regs
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v11_0.c3381 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local
3387 if (disp_int & interrupt_status_offsets[crtc].vblank)
3399 if (disp_int & interrupt_status_offsets[crtc].vline)
3419 uint32_t disp_int, mask; local
3428 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3431 if (disp_int & mask) {
H A Ddce_v10_0.c3250 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local
3255 if (disp_int & interrupt_status_offsets[crtc].vblank)
3267 if (disp_int & interrupt_status_offsets[crtc].vline)
3287 uint32_t disp_int, mask; local
3296 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3299 if (disp_int & mask) {
H A Ddce_v8_0.c3084 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local
3090 if (disp_int & interrupt_status_offsets[crtc].vblank)
3101 if (disp_int & interrupt_status_offsets[crtc].vline)
3196 uint32_t disp_int, mask; local
3205 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3208 if (disp_int & mask) {
H A Ddce_v6_0.c2996 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local
3002 if (disp_int & interrupt_status_offsets[crtc].vblank)
3013 if (disp_int & interrupt_status_offsets[crtc].vline)
3108 uint32_t disp_int, mask; local
3117 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3120 if (disp_int & mask) {

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