Searched refs:desc_base (Results 1 - 16 of 16) sorted by relevance

/linux-master/arch/mips/include/asm/mach-lantiq/xway/
H A Dxway_dma.h30 struct ltq_dma_desc *desc_base; /* the descriptor base */ member in struct:ltq_dma_channel
/linux-master/drivers/net/ethernet/sunplus/
H A Dspl2sw_desc.c108 if (comm->desc_base) {
109 dma_free_coherent(&comm->pdev->dev, comm->desc_size, comm->desc_base,
111 comm->desc_base = NULL;
179 comm->desc_base = dma_alloc_coherent(&comm->pdev->dev, desc_size, &comm->desc_dma,
181 if (!comm->desc_base)
187 comm->tx_desc = comm->desc_base;
H A Dspl2sw_define.h229 void *desc_base; member in struct:spl2sw_common
/linux-master/drivers/net/ethernet/
H A Dlantiq_xrx200.c135 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
210 ch->dma.desc_base[ch->dma.desc].addr = mapping + NET_SKB_PAD + NET_IP_ALIGN;
214 ch->dma.desc_base[ch->dma.desc].ctl =
223 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
291 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
323 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free];
332 memset(&ch->dma.desc_base[ch->tx_free], 0,
362 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
H A Dlantiq_etop.c114 ch->dma.desc_base[ch->dma.desc].addr =
117 ch->dma.desc_base[ch->dma.desc].addr =
119 ch->dma.desc_base[ch->dma.desc].ctl =
130 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
158 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
183 while ((ch->dma.desc_base[ch->tx_free].ctl &
187 memset(&ch->dma.desc_base[ch->tx_free], 0,
480 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
510 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
/linux-master/arch/mips/lantiq/xway/
H A Ddma.c127 ch->desc_base = dma_alloc_coherent(ch->dev,
176 if (!ch->desc_base)
180 ch->desc_base, ch->phys);
/linux-master/arch/mips/alchemy/common/
H A Ddbdma.c394 u32 desc_base, srcid, destid; local
415 desc_base = (u32)kmalloc_array(entries, sizeof(au1x_ddma_desc_t),
417 if (desc_base == 0)
420 if (desc_base & 0x1f) {
425 kfree((const void *)desc_base);
428 desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA);
429 if (desc_base == 0)
432 ctp->cdb_membase = desc_base;
433 desc_base = ALIGN_ADDR(desc_base, sizeo
[all...]
/linux-master/drivers/mmc/host/
H A Dcqhci-core.c38 return cq_host->desc_base + (tag * cq_host->slot_sz);
215 cq_host->desc_base = dmam_alloc_coherent(mmc_dev(cq_host->mmc),
219 if (!cq_host->desc_base)
228 cq_host->desc_base,
230 cq_host->desc_base = NULL;
236 mmc_hostname(cq_host->mmc), cq_host->desc_base, cq_host->trans_desc_base,
413 cq_host->desc_base,
417 cq_host->desc_base = NULL;
H A Dcqhci.h253 u8 *desc_base; member in struct:cqhci_host
/linux-master/drivers/net/ethernet/mediatek/
H A Dmtk_wed_wo.c325 mtk_wed_mmio_w32(wo, q->regs.desc_base, q->desc_dma);
406 regs.desc_base = MTK_WED_WO_CCIF_DUMMY1;
420 regs.desc_base = MTK_WED_WO_CCIF_DUMMY5;
H A Dmtk_wed_wo.h193 u32 desc_base; member in struct:mtk_wed_wo_queue_regs
/linux-master/arch/x86/lib/
H A Dinsn-eval.c624 unsigned long desc_base; local
655 desc_base = sel & ~(SEGMENT_RPL_MASK | SEGMENT_TI_MASK);
657 if (desc_base > gdt_desc.size)
660 *out = *(struct desc_struct *)(gdt_desc.address + desc_base);
/linux-master/drivers/dma/lgm/
H A Dlgm-dma.c202 void *desc_base; /* Virtual address */ member in struct:ldma_chan
635 static void ldma_chan_desc_hw_cfg(struct ldma_chan *c, dma_addr_t desc_base, argument
643 writel(lower_32_bits(desc_base), d->base + DMA_CDBA);
647 u32 hi = upper_32_bits(desc_base) & HIGH_4_BITS;
659 ldma_chan_desc_cfg(struct dma_chan *chan, dma_addr_t desc_base, int desc_num) argument
678 ldma_chan_desc_hw_cfg(c, desc_base, desc_num);
682 c->desc_phys = desc_base;
/linux-master/drivers/atm/
H A Diphase.h676 ffreg_t desc_base; /* Base address of descriptor table */ member in struct:_ffredn_t
730 rreg_t desc_base; /* Base address for description table */ member in struct:_rfredn_t
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Ddma.c191 Q_WRITE(q, desc_base, q->desc_dma);
H A Dmt76.h195 u32 desc_base; member in struct:mt76_queue_regs

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