Searched refs:dcore_offset (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/accel/habanalabs/common/
H A Dsecurity.c298 * @dcore_offset: offset between dcores
308 u32 dcore_offset, u32 num_instances, u32 instance_offset,
334 i * dcore_offset + j * instance_offset,
350 * @dcore_offset: offset between dcores
359 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, argument
364 return hl_init_pb_with_mask(hdev, num_dcores, dcore_offset,
378 * @dcore_offset: offset between dcores
388 u32 dcore_offset, u32 num_instances, u32 instance_offset,
418 i * dcore_offset + j * instance_offset,
436 * @dcore_offset
307 hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const u32 *user_regs_array, u32 user_regs_array_size, u64 mask) argument
387 hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size, u64 mask) argument
445 hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size) argument
471 hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const u32 *user_regs_array, u32 user_regs_array_size) argument
519 hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size) argument
563 hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, u64 mask) argument
597 hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size) argument
618 hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size) argument
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H A Dhabanalabs.h4173 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4176 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4181 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4186 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4190 int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4194 int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4199 void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4203 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4205 void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c7620 u32 dcore_offset = dcore_id * DCORE_OFFSET; local
7627 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);
7628 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);
7629 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);
7630 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);
7634 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0);
7635 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid);
7636 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid);
7637 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0);
7641 WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asi
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