Searched refs:d6 (Results 1 - 25 of 47) sorted by path

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/arm/
H A Ddsputil_neon_s.S36 vld1.64 {d6, d7}, [r1], r2
54 vst1.64 {d6, d7}, [r0,:128], r2
61 vld1.64 {d4-d6}, [r1], r2
89 vst1.64 {d6, d7}, [r0,:128], r2
99 vld1.64 {d4-d6}, [ip], lr
109 vaddl.u8 q9, d4, d6
213 vext.8 d6, d2, d3, #1
215 vaddl.u8 q9, d2, d6
234 vext.8 d6, d2, d3, #1
235 vaddl.u8 q9, d2, d6
[all...]
H A Dh264dsp_neon.S85 vld1.64 {d6, d7}, [r5], r4
89 vext.8 d7, d6, d7, #1
95 vmlal.u8 q8, d6, d2
98 vmull.u8 q9, d6, d0
104 vld1.64 {d6, d7}, [r5], r4
112 vext.8 d7, d6, d7, #1
129 vld1.64 {d6}, [r5], r4
133 vmlal.u8 q8, d6, d1
135 vmull.u8 q9, d6, d0
137 vld1.64 {d6}, [r
[all...]
H A Dh264idct_neon.S39 vadd.i16 d6, d2, d17
56 vadd.i16 d6, d16, d3
H A Dsimple_idct_neon.S51 vmull.s16 q7, d6, w2 /* q9 = W2 * col[2] */
52 vmull.s16 q8, d6, w6 /* q10 = W6 * col[2] */
75 vld1.64 {d6,d7}, [r2,:128]!
116 vshrn.i32 d6, q7, #ROW_SHIFT
120 vtrn.16 d6, d8
123 vtrn.32 d2, d6
136 vst1.64 {d6-d9}, [r2,:128]!
147 vld1.64 {d6}, [r2,:64], ip /* d4 = col[2] */
159 vld1.64 {d3}, [r2,:64], ip /* d6 = col[4] */
207 vsubhn.i32 d6, q1
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/
H A Deaidct.c35 #define IDCT_TRANSFORM(dest,s0,s1,s2,s3,s4,s5,s6,s7,d0,d1,d2,d3,d4,d5,d6,d7,munge,src) {\
54 (dest)[d6] = munge(a4+a6 -b1); \
H A Djrevdct.c217 int32_t d0, d1, d2, d3, d4, d5, d6, d7; local
244 d6 = dataptr[3];
250 if ((d1 | d2 | d3 | d4 | d5 | d6 | d7) == 0) {
270 if (d6) {
272 /* d0 != 0, d2 != 0, d4 != 0, d6 != 0 */
273 z1 = MULTIPLY(d2 + d6, FIX_0_541196100);
274 tmp2 = z1 + MULTIPLY(-d6, FIX_1_847759065);
285 /* d0 != 0, d2 == 0, d4 != 0, d6 != 0 */
286 tmp2 = MULTIPLY(-d6, FIX_1_306562965);
287 tmp3 = MULTIPLY(d6, FIX_0_54119610
957 int32_t d0, d2, d4, d6; local
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/ppc/
H A Dh264_altivec.c480 #define IDCT8_1D_ALTIVEC(s0, s1, s2, s3, s4, s5, s6, s7, d0, d1, d2, d3, d4, d5, d6, d7) {\
529 d6 = vec_sub(b2v, b5v); \
557 vec_s16 d0, d1, d2, d3, d4, d5, d6, d7; local
582 d0, d1, d2, d3, d4, d5, d6, d7);
584 TRANSPOSE8( d0, d1, d2, d3, d4, d5, d6, d7 );
586 IDCT8_1D_ALTIVEC(d0, d1, d2, d3, d4, d5, d6, d7,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/mtools-4.0.10/
H A Dtexinfo.tex8161 \gdef^^d6{\"O}
8281 \gdef^^d6{\"O}
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/gettext-0.17/build-aux/
H A Dtexinfo.tex7889 \gdef^^d6{\"O}
8009 \gdef^^d6{\"O}
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/libgcrypt-1.5.0/mpi/m68k/
H A Dmpih-lshift.S43 #define s_size d6
54 moveml R(d2)-R(d6)/R(a2),MEM_PREDEC(sp)
125 moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
157 moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
H A Dmpih-rshift.S43 #define s_size d6
53 moveml R(d2)-R(d6)/R(a2),MEM_PREDEC(sp)
114 moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
156 moveml MEM_POSTINC(sp),R(d2)-R(d6)/R(a2)
H A Dsyntax.h120 #define d6 D6 macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/fpsp040/
H A Dbindec.S34 | This value is stored in d6.
118 | d6: ILOG
220 | in d6.
229 | d6: x/ILOG
244 movel #-4933,%d6 |force ILOG = -4933
255 fmovel %fp0,%d6 |put ILOG in d6 as a lword
259 fmovel %fp0,%d6 |put ILOG in d6 as a lword
292 | d6
[all...]
H A Dbinstr.S43 | A7. Decrement d6 (LEN counter) and repeat the loop until zero.
55 | d6: temp for bit-field extracts
91 bfextu %d3{#0:#3},%d6 |copy 3 msbs of d3 into d6
93 orl %d6,%d2 |or in msbs from d3 into d2
99 swap %d6 |put 0 in d6 lower word
100 addxw %d6,%d1 |add in extend from mul by 2
108 addxw %d6,%d1 |add in extend from add to d1
109 swap %d6 |wit
[all...]
H A Dres_func.S2033 movel %d6,%d0
H A Dround.S311 moveml %d2/%d3/%d5/%d6,-(%a7)
322 moveml (%a7)+,%d2/%d3/%d5/%d6
325 movel %d2,%d6 |save ls mant in d6
330 lsrl %d5,%d6 |by the number in the exp, then
332 orl %d6,%d1 |shift the ls mant bits into the ms mant
338 moveml (%a7)+,%d2/%d3/%d5/%d6
347 moveml (%a7)+,%d2/%d3/%d5/%d6
351 moveml (%a7)+,%d2/%d3/%d5/%d6
362 movel %d6,
[all...]
H A Dsgetem.S126 moveml %d3/%d5/%d6,-(%a7) |save registers
129 movel %d1,%d6 |save ls mant in d6
133 lsrl %d5,%d6 |shift off all bits but those that will
135 orl %d6,%d0 |shift the ls mant bits into the ms mant
136 moveml (%a7)+,%d3/%d5/%d6 |restore registers
H A Dsrem_mod.S130 clrl %d6
131 bfffo %d4{#0:#32},%d6
132 lsll %d6,%d4
133 subl %d6,%d3 | ...(D3,D4,D5) is normalized
138 clrl %d6
139 bfffo %d4{#0:#32},%d6
140 subl %d6,%d3
141 lsll %d6,%d4
143 lsll %d6,%d5
144 negl %d6
[all...]
H A Dutil.S694 moveb L_SCR1(%a6),%d6
718 movew L_SCR1(%a6),%d6
742 movel L_SCR1(%a6),%d6
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/ifpsp060/src/
H A Dfplsp.S8402 clr.l %d6
8403 bfffo %d4{&0:&32},%d6
8404 lsl.l %d6,%d4
8405 add.l %d6,%d2 # (D3,D4,D5) is normalized
8418 clr.l %d6
8419 bfffo %d4{&0:&32},%d6 # find first 1
8420 mov.l %d6,%d2 # get k
8421 lsl.l %d6,%d4
8423 lsl.l %d6,%d5
8424 neg.l %d6
[all...]
H A Dfpsp.S8508 clr.l %d6
8509 bfffo %d4{&0:&32},%d6
8510 lsl.l %d6,%d4
8511 add.l %d6,%d2 # (D3,D4,D5) is normalized
8524 clr.l %d6
8525 bfffo %d4{&0:&32},%d6 # find first 1
8526 mov.l %d6,%d2 # get k
8527 lsl.l %d6,%d4
8529 lsl.l %d6,%d5
8530 neg.l %d6
[all...]
H A Dilsp.S139 mov.l 0x10(%a6), %d6 # get dividend lo
160 negx.l %d6 # complement signed dividend
170 tst.l %d6 # is (lo(dividend) == 0), too
173 cmp.l %d7,%d6 # is (divisor <= lo(dividend))
176 exg %d5,%d6 # q = 0, r = dividend
180 tdivu.l %d7, %d5:%d6 # it's only a 32/32 bit div!
209 cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits?
212 neg.l %d6 # make (-quot) 2's comp
217 btst &0x1f, %d6 # will (+quot) fit in 32 bits?
225 tst.l %d6 # ma
[all...]
H A Ditest.S1468 mov.l (%a1),%d6
1501 mov.l (%a1),%d6
1534 mov.l (%a1),%d6
1567 mov.l (%a1),%d6
1602 mov.l (%a1),%d6
1637 mov.l (%a1),%d6
1672 mov.l (%a1),%d6
1707 mov.l (%a1),%d6
1742 mov.l (%a1),%d6
1778 mov.w (%a1),%d6
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/kernel/
H A Dhead.S1655 movel %a0@+,%d6
1656 btst #1,%d6
1662 andil #0xfffffe00,%d6
1663 movel %d6,%a1
1667 movel %a1@+,%d6
1668 btst #1,%d6
1674 andil #0xffffff00,%d6
1675 movel %d6,%a2
1679 movel %a2@+,%d6
1680 btst #0,%d6
[all...]
H A Dprocess.c344 dump->regs.d6 = sw->d6;

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