/haiku/src/add-ons/accelerants/radeon/ |
H A D | palette.c | 22 accelerator_info *ai, int crtc_idx ) 30 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) | 42 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) | 54 accelerator_info *ai, int crtc_idx, 81 accelerator_info *ai, int crtc_idx, 90 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) | 105 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) | 80 setPalette( accelerator_info *ai, int crtc_idx, uint count, uint8 first, uint8 *color_data ) argument
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H A D | radeon_accelerant.h | 100 status_t Radeon_SetDPMS( accelerator_info *ai, int crtc_idx, int mode ); 101 uint32 Radeon_GetDPMS( accelerator_info *ai, int crtc_idx ); 105 void Radeon_SetCursorColors( accelerator_info *ai, int crtc_idx ); 106 void Radeon_ShowCursor( accelerator_info *ai, int crtc_idx ); 134 void Radeon_InitOverlay( accelerator_info *ai, int crtc_idx ); 146 void Radeon_InitPalette( accelerator_info *ai, int crtc_idx );
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H A D | Cursor.c | 17 static void moveOneCursor( accelerator_info *ai, int crtc_idx, int x, int y ); 20 void Radeon_SetCursorColors( accelerator_info *ai, int crtc_idx ) 24 if( crtc_idx == 0 ) { 151 void moveOneCursor( accelerator_info *ai, int crtc_idx, int x, int y ) argument 154 crtc_info *crtc = &ai->si->crtc[crtc_idx]; 180 Radeon_ShowCursor( ai, crtc_idx ); 196 if( crtc_idx == 0 ) { 220 void Radeon_ShowCursor( accelerator_info *ai, int crtc_idx ) 223 crtc_info *crtc = &ai->si->crtc[crtc_idx]; 226 if( crtc_idx [all...] |
H A D | pll.c | 21 accelerator_info *ai, int crtc_idx ) 29 if( (Radeon_INPLL( ai->regs, ai->si->asic, crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV ) 36 accelerator_info *ai, int crtc_idx ) 38 Radeon_PLLWaitForReadUpdateComplete( ai, crtc_idx ); 41 crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV, 455 accelerator_info *ai, int crtc_idx, pll_regs *values ) 464 Radeon_OUTPLLP( regs, asic, crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL, 468 crtc_idx == 0 ? RADEON_PPLL_CNTL : RADEON_P2PLL_CNTL, 483 if( ai->si->new_pll && crtc_idx == 0 ) { 493 crtc_idx 454 Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values ) argument [all...] |
H A D | dpms.c | 291 status_t Radeon_SetDPMS( accelerator_info *ai, int crtc_idx, int mode ) argument 293 crtc_info *crtc = &ai->si->crtc[crtc_idx]; 306 if( crtc_idx == 0 ) 317 if( crtc_idx == 0 || 1/* && (crtc->active_displays & dd_crt) != 0 */) 320 if( crtc_idx == 1 || (crtc->active_displays & (dd_tv_crt | dd_ctv | dd_stv)) != 0 ) 381 uint32 Radeon_GetDPMS( accelerator_info *ai, int crtc_idx ) 383 if( crtc_idx == 0 )
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H A D | overlay.c | 54 accelerator_info *ai, int crtc_idx ) 96 if( si->crtc[crtc_idx].mode.timing.pixel_clock < 175000 ) 112 si->active_overlay.crtc_idx = si->pending_overlay.crtc_idx; 530 accelerator_info *ai, int crtc_idx ) 537 crtc_info *crtc = &si->crtc[crtc_idx]; 863 crtc->crtc_idx == 0 ? RADEON_OV0_Y_X_START : RADEON_OV1_Y_X_START, 866 crtc->crtc_idx == 0 ? RADEON_OV0_Y_X_END : RADEON_OV1_Y_X_END, 891 (crtc->crtc_idx == 0 ? 0 : RADEON_SCALER_CRTC_SEL ); 955 si->active_overlay.crtc_idx 1067 int crtc_idx; local [all...] |
H A D | monitor_routing.c | 128 int crtc_idx = (display_devices[1] & dd_crt) != 0; local 142 values->dac_cntl2 |= crtc_idx == 0 ? 0 : RADEON_DAC_CLK_SEL_CRTC2; 153 (crtc_idx == 0 ? 0 : RADEON_DISP_DAC_SOURCE_CRTC2); 293 int crtc_idx = (display_devices[1] & (dd_tv_crt | dd_ctv | dd_stv)) != 0; local 305 values->disp_hw_debug |= crtc_idx == 0 ? RADEON_CRT2_DISP1_SEL : 0; 313 values->disp_tv_out_cntl |= crtc_idx == 0 ? 0 : RADEON_DISP_TV_PATH_SRC; 323 crtc_idx == 0 ? 0 : RADEON_DISP_TVDAC_SOURCE_CRTC2; 333 int crtc_idx = (display_devices[1] & (dd_ctv | dd_stv)) != 0; local 336 values->pixclks_cntl |= crtc_idx == 0 ? 378 int crtc_idx local 395 int crtc_idx = (display_devices[1] & (dd_dvi_ext)) != 0; local [all...] |
H A D | crtc.c | 19 void Radeon_ProgramCRTCRegisters( accelerator_info *ai, int crtc_idx, argument 26 if( crtc_idx == 0 ) { 80 if( crtc->crtc_idx == 0 ) { 141 offset, crtc->crtc_idx ); 143 OUTREG( ai->regs, crtc->crtc_idx == 0 ? RADEON_CRTC_OFFSET : RADEON_CRTC2_OFFSET, offset );
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H A D | set_mode.h | 210 void Radeon_ProgramCRTCRegisters( accelerator_info *ai, int crtc_idx, 217 void Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values ); 268 impactv_params *params, impactv_regs *values, int crtc_idx,
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H A D | SetDisplayMode.c | 205 if( crtc->crtc_idx == 0 ) 228 crtc->crtc_idx, internal_tv_encoder, vc->tv_standard, disp_devices ); 246 if( crtc->crtc_idx == 0 ) 261 Radeon_ProgramCRTCRegisters( ai, crtc->crtc_idx, &crtc_values ); 265 if( crtc->crtc_idx == 0 ) 272 Radeon_ProgramPLL( ai, crtc->crtc_idx, &pll_values ); 311 si->active_overlay.crtc_idx = -1;
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H A D | InitAccelerant.c | 195 si->active_overlay.crtc_idx = -1; 196 si->pending_overlay.crtc_idx = -1;
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H A D | impactv.c | 418 impactv_params *params, impactv_regs *values, int crtc_idx, 660 ((crtc_idx == 1 ? 2 : 0) << RADEON_TV_RGB_CNTL_RGB_SRC_SEL_SHIFT) | 416 Radeon_CalcImpacTVRegisters( accelerator_info *ai, display_mode *mode, impactv_params *params, impactv_regs *values, int crtc_idx, bool internal_encoder, tv_standard_e tv_format, display_device_e display_device ) argument
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/haiku/headers/private/graphics/radeon/ |
H A D | radeon_interface.h | 307 int crtc_idx; // index of CRTC member in struct:__anon19 376 int crtc_idx; // crtc where the overlay is shown on member in struct:__anon24
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/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | init.c | 265 si->crtc[0].crtc_idx = 0; 267 si->crtc[1].crtc_idx = 1;
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