Searched refs:control_value (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_drv.c133 u32 control_value = 0; local
143 control_value = readl(mmio + HIBMC_POWER_MODE_CTRL);
144 control_value &= ~(HIBMC_PW_MODE_CTL_MODE_MASK |
146 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_MODE, power_mode);
147 control_value |= HIBMC_FIELD(HIBMC_PW_MODE_CTL_OSC_INPUT, input);
148 writel(control_value, mmio + HIBMC_POWER_MODE_CTRL);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_mocs.c34 u32 control_value; member in struct:xe_mocs_entry
112 .control_value = __control_value, \
454 * Get control_value from MOCS entry. If the table entry is not defined, the
461 return info->table[index].control_value;
462 return info->table[info->unused_entries_index].control_value;
/linux-master/drivers/mmc/host/
H A Dsdhci-pci-gli.c271 u32 control_value; local
281 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
320 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
321 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
322 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
324 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
336 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
337 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
339 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
345 control_value
[all...]
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_mocs.c17 u32 control_value; member in struct:drm_i915_mocs_entry
89 .control_value = __control_value, \
587 * Get control_value from MOCS entry taking into account when it's not used
595 return table->table[index].control_value;
596 return table->table[table->unused_entries_index].control_value;
/linux-master/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic.h1421 u32 control_value; member in union:netxen_minidump_entry_crb::__anon1467
1496 u32 control_value; member in union:netxen_minidump_entry_cache::__anon1483

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