/linux-master/sound/pci/echoaudio/ |
H A D | echoaudio_3g.c | 145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) argument 147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; 151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; 155 control_reg |= E3G_SPDIF_SAMPLE_RATE0; 158 control_reg |= E3G_SPDIF_SAMPLE_RATE1; 163 control_reg |= E3G_SPDIF_PRO_MODE; 166 control_reg |= E3G_SPDIF_NOT_AUDIO; 168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | 171 return control_reg; 179 u32 control_reg; local 260 u32 control_reg, clock, base_rate, frq_reg; local 330 u32 control_reg, clocks_from_dsp; local 378 u32 control_reg; local [all...] |
H A D | gina24_dsp.c | 126 u32 control_reg; local 156 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; 157 err = write_control_reg(chip, control_reg, true); 166 u32 control_reg, clock; local 184 control_reg = le32_to_cpu(chip->comm_page->control_register); 185 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; 200 if (control_reg & GML_SPDIF_PRO_MODE) 225 control_reg |= clock; 231 return write_control_reg(chip, control_reg, false); 238 u32 control_reg, clocks_from_ds local 286 u32 control_reg; local [all...] |
H A D | layla24_dsp.c | 162 u32 control_reg, clock, base_rate; local 179 control_reg = le32_to_cpu(chip->comm_page->control_register); 180 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; 197 if (control_reg & GML_SPDIF_PRO_MODE) 222 control_reg |= GML_DOUBLE_SPEED_MODE; 240 control_reg |= clock; 245 "set_sample_rate: %d clock %d\n", rate, control_reg); 247 return write_control_reg(chip, control_reg, false); 254 u32 control_reg, clocks_from_dsp; local 257 control_reg 335 u32 control_reg; local [all...] |
H A D | echoaudio_gml.c | 158 u32 control_reg; local 162 control_reg = le32_to_cpu(chip->comm_page->control_register); 163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; 166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | 170 control_reg |= GML_SPDIF_PRO_MODE; 174 control_reg |= GML_SPDIF_SAMPLE_RATE0 | 178 control_reg |= GML_SPDIF_SAMPLE_RATE0; 181 control_reg |= GML_SPDIF_SAMPLE_RATE1; 188 control_reg |= GML_SPDIF_SAMPLE_RATE0 | 192 control_reg | [all...] |
H A D | mona_dsp.c | 119 u32 control_reg; local 152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; 153 err = write_control_reg(chip, control_reg, true); 200 u32 control_reg, clock; local 246 control_reg = le32_to_cpu(chip->comm_page->control_register); 247 control_reg &= GML_CLOCK_CLEAR_MASK; 248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; 263 if (control_reg & GML_SPDIF_PRO_MODE) 288 control_reg |= clock; 295 return write_control_reg(chip, control_reg, force_writ 302 u32 control_reg, clocks_from_dsp; local 363 u32 control_reg; local [all...] |
H A D | indigo_express_dsp.c | 31 u32 clock, control_reg, old_control_reg; local 37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; 62 control_reg |= clock; 63 if (control_reg != old_control_reg) { 66 chip->comm_page->control_register = cpu_to_le32(control_reg);
|
H A D | indigodj_dsp.c | 94 u32 control_reg; local 98 control_reg = MIA_96000; 101 control_reg = MIA_88200; 104 control_reg = MIA_48000; 107 control_reg = MIA_44100; 110 control_reg = MIA_32000; 119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { 124 chip->comm_page->control_register = cpu_to_le32(control_reg);
|
H A D | indigo_dsp.c | 94 u32 control_reg; local 98 control_reg = MIA_96000; 101 control_reg = MIA_88200; 104 control_reg = MIA_48000; 107 control_reg = MIA_44100; 110 control_reg = MIA_32000; 119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { 124 chip->comm_page->control_register = cpu_to_le32(control_reg);
|
H A D | mia_dsp.c | 111 u32 control_reg; local 115 control_reg = MIA_96000; 118 control_reg = MIA_88200; 121 control_reg = MIA_48000; 124 control_reg = MIA_44100; 127 control_reg = MIA_32000; 137 control_reg |= MIA_SPDIF; 140 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { 145 chip->comm_page->control_register = cpu_to_le32(control_reg);
|
H A D | echo3g_dsp.c | 121 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); local 124 control_reg |= E3G_PHANTOM_POWER; 126 control_reg &= ~E3G_PHANTOM_POWER; 129 return write_control_reg(chip, control_reg,
|
/linux-master/drivers/scsi/pcmcia/ |
H A D | nsp_message.c | 15 unsigned char data_reg, control_reg; local 33 control_reg = nsp_index_read(base, SCSIBUSCTRL); 34 control_reg |= SCSI_ACK; 35 nsp_index_write(base, SCSIBUSCTRL, control_reg); 41 control_reg = nsp_index_read(base, SCSIBUSCTRL); 42 control_reg &= ~SCSI_ACK; 43 nsp_index_write(base, SCSIBUSCTRL, control_reg);
|
/linux-master/drivers/clk/ |
H A D | clk-palmas.c | 26 unsigned int control_reg; member in struct:palmas_clk32k_desc 58 cinfo->clk_desc->control_reg, 63 cinfo->clk_desc->control_reg, ret); 83 cinfo->clk_desc->control_reg, 87 cinfo->clk_desc->control_reg, ret); 100 cinfo->clk_desc->control_reg, &val); 103 cinfo->clk_desc->control_reg, ret); 129 .control_reg = PALMAS_CLK32KG_CTRL, 145 .control_reg = PALMAS_CLK32KGAUDIO_CTRL, 202 cinfo->clk_desc->control_reg, [all...] |
/linux-master/drivers/watchdog/ |
H A D | ts72xx_wdt.c | 29 /* priv->control_reg */ 43 void __iomem *control_reg; member in struct:ts72xx_wdt_priv 54 writeb(priv->regval, priv->control_reg); 64 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); 132 priv->control_reg = devm_platform_ioremap_resource(pdev, 0); 133 if (IS_ERR(priv->control_reg)) 134 return PTR_ERR(priv->control_reg);
|
/linux-master/drivers/clk/ti/ |
H A D | apll.c | 55 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 58 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 94 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 97 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 108 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 212 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); 241 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 267 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 270 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 297 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); [all...] |
H A D | dpll3xxx.c | 54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); 57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); 308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); 373 ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); 399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); 402 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); 456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); 472 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); 860 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask; 884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); [all...] |
H A D | clkt_dpll.c | 213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); 249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
|
/linux-master/arch/mips/cavium-octeon/executive/ |
H A D | cvmx-helper-sgmii.c | 139 union cvmx_pcsx_mrx_control_reg control_reg; local 149 control_reg.u64 = 152 control_reg.s.reset = 1; 154 control_reg.u64); 169 control_reg.s.rst_an = 1; 170 control_reg.s.an_en = 1; 171 control_reg.s.pwr_dn = 0; 173 control_reg.u64);
|
/linux-master/drivers/tty/serial/ |
H A D | pmac_zilog.h | 54 volatile u8 __iomem *control_reg; member in struct:uart_pmac_port 78 writeb(reg, port->control_reg); 79 return readb(port->control_reg); 85 writeb(reg, port->control_reg); 86 writeb(value, port->control_reg); 101 (void)readb(port->control_reg);
|
/linux-master/drivers/power/supply/ |
H A D | ds2780_battery.c | 357 u8 *control_reg) 359 return ds2780_read8(dev_info, control_reg, DS2780_CONTROL_REG); 363 u8 control_reg) 367 ret = ds2780_write(dev_info, &control_reg, 448 u8 control_reg; local 453 ret = ds2780_get_control_register(dev_info, &control_reg); 458 !!(control_reg & DS2780_CONTROL_REG_PMOD)); 467 u8 control_reg, new_setting; local 472 ret = ds2780_get_control_register(dev_info, &control_reg); 486 control_reg | 356 ds2780_get_control_register(struct ds2780_device_info *dev_info, u8 *control_reg) argument 362 ds2780_set_control_register(struct ds2780_device_info *dev_info, u8 control_reg) argument [all...] |
H A D | ds2781_battery.c | 359 u8 *control_reg) 361 return ds2781_read8(dev_info, control_reg, DS2781_CONTROL); 365 u8 control_reg) 369 ret = ds2781_write(dev_info, &control_reg, 450 u8 control_reg; local 455 ret = ds2781_get_control_register(dev_info, &control_reg); 460 !!(control_reg & DS2781_CONTROL_PMOD)); 469 u8 control_reg, new_setting; local 474 ret = ds2781_get_control_register(dev_info, &control_reg); 488 control_reg | 358 ds2781_get_control_register(struct ds2781_device_info *dev_info, u8 *control_reg) argument 364 ds2781_set_control_register(struct ds2781_device_info *dev_info, u8 control_reg) argument [all...] |
/linux-master/drivers/regulator/ |
H A D | anatop-regulator.c | 166 u32 control_reg; local 203 ret = of_property_read_u32(np, "anatop-reg-offset", &control_reg); 247 rdesc->vsel_reg = control_reg; 258 if (control_reg && sreg->delay_bit_width) { 300 rdesc->enable_reg = control_reg;
|
H A D | as3722-regulator.c | 55 u32 control_reg; member in struct:as3722_register_mapping 85 .control_reg = AS3722_SD0_CONTROL_REG, 97 .control_reg = AS3722_SD1_CONTROL_REG, 110 .control_reg = AS3722_SD23_CONTROL_REG, 124 .control_reg = AS3722_SD23_CONTROL_REG, 138 .control_reg = AS3722_SD4_CONTROL_REG, 152 .control_reg = AS3722_SD5_CONTROL_REG, 165 .control_reg = AS3722_SD6_CONTROL_REG, 427 if (!as3722_reg_lookup[id].control_reg) 430 ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, [all...] |
H A D | ti-abb-regulator.c | 78 * @control_reg: control register of ABB block 96 void __iomem *control_reg; member in struct:ti_abb 261 ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg); 272 ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg); 717 abb->control_reg = abb->base + abb->regs->control_off; 720 abb->control_reg = devm_platform_ioremap_resource_byname(pdev, "control-address"); 721 if (IS_ERR(abb->control_reg)) 722 return PTR_ERR(abb->control_reg);
|
/linux-master/drivers/staging/fieldbus/anybuss/ |
H A D | arcx-anybus.c | 45 u8 control_reg; member in struct:controller_priv 55 * cd->control_reg 58 cd->control_reg &= ~rst_bit; 60 cd->control_reg |= rst_bit; 61 writeb(cd->control_reg, cd->cpld_base + CPLD_CONTROL);
|
/linux-master/drivers/i2c/busses/ |
H A D | i2c-mt65xx.c | 554 u16 control_reg; local 632 control_reg = I2C_CONTROL_ACKERR_DET_EN | 635 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE; 637 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL); 1002 u16 control_reg; local 1042 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & 1045 control_reg |= I2C_CONTROL_RS; 1048 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; 1050 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
|