| /linux-master/drivers/infiniband/hw/bnxt_re/ |
| H A D | qplib_tlv.h | 48 static inline u8 __get_cmdq_base_opcode(struct cmdq_base *req, u32 size)
51 return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode;
56 static inline void __set_cmdq_base_opcode(struct cmdq_base *req,
60 ((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val;
65 static inline __le16 __get_cmdq_base_cookie(struct cmdq_base *req, u32 size)
68 return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie;
73 static inline void __set_cmdq_base_cookie(struct cmdq_base *req,
77 ((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val;
82 static inline __le64 __get_cmdq_base_resp_addr(struct cmdq_base *req, u32 size)
85 return ((struct cmdq_base *)GET_TLV_DAT
[all...] |
| H A D | qplib_rcfw.h | 63 static inline void bnxt_qplib_rcfw_cmd_prep(struct cmdq_base *req,
97 static inline u32 bnxt_qplib_get_cmd_slots(struct cmdq_base *req)
113 static inline u32 bnxt_qplib_set_cmd_slots(struct cmdq_base *req)
238 struct cmdq_base *req;
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| H A D | qplib_sp.c | 77 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
103 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
190 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
259 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
328 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
391 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
430 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
475 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
501 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
536 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)
[all...] |
| H A D | qplib_rcfw.c | 458 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
462 msg.req = (struct cmdq_base *)&req;
816 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
838 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
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| H A D | qplib_fp.c | 610 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
653 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
731 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
842 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
990 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1278 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1392 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
1522 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
2152 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req,
2219 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)
[all...] |
| H A D | roce_hsi.h | 103 /* cmdq_base (size:128b/16B) */
104 struct cmdq_base { struct
|
| /linux-master/drivers/gpu/drm/mediatek/ |
| H A D | mtk_ethdr.c | 72 struct cmdq_client_reg cmdq_base; member in struct:mtk_ethdr_comp
164 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
176 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
178 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
179 mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
181 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
199 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
202 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
205 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
208 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
[all...] |
| /linux-master/drivers/soc/mediatek/ |
| H A D | mtk-mmsys.c | 160 struct cmdq_client_reg cmdq_base; member in struct:mtk_mmsys
169 if (mmsys->cmdq_base.size && cmdq_pkt) {
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
171 mmsys->cmdq_base.offset + offset, val,
422 ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
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| /linux-master/drivers/accel/ivpu/ |
| H A D | vpu_jsm_api.h | 754 u64 cmdq_base; member in struct:vpu_ipc_msg_payload_hws_create_cmdq
818 * and cmdq_base and cmdq_size will be used. For HW scheduling, cmdq_base and cmdq_size will be
830 u64 cmdq_base; member in struct:vpu_jsm_hws_register_db
|