/linux-master/arch/arm64/kvm/hyp/nvhe/ |
H A D | timer-sr.c | 42 u64 clr = 0, set = 0; local 49 clr = CNTHCTL_EL1PCEN; 54 clr |= CNTHCTL_EL1PCTEN; 57 clr <<= 10; 61 sysreg_clear_set(cnthctl_el2, clr, set);
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/linux-master/include/trace/events/ |
H A D | thp.h | 40 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set), 41 TP_ARGS(addr, pte, clr, set), 45 __field(unsigned long, clr) 52 __entry->clr = clr; 57 TP_printk("hugepage update at addr 0x%lx and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, __entry->clr, __entry->set) 61 TP_PROTO(unsigned long addr, unsigned long pmd, unsigned long clr, unsigned long set), 62 TP_ARGS(addr, pmd, clr, set) 66 TP_PROTO(unsigned long addr, unsigned long pud, unsigned long clr, unsigne [all...] |
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
H A D | dr_ste.c | 806 static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec, bool clr) argument 808 spec->gre_c_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_c_present, clr); 809 spec->gre_k_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_k_present, clr); 810 spec->gre_s_present = IFC_GET_CLR(fte_match_set_misc, mask, gre_s_present, clr); 811 spec->source_vhca_port = IFC_GET_CLR(fte_match_set_misc, mask, source_vhca_port, clr); 812 spec->source_sqn = IFC_GET_CLR(fte_match_set_misc, mask, source_sqn, clr); 814 spec->source_port = IFC_GET_CLR(fte_match_set_misc, mask, source_port, clr); 816 IFC_GET_CLR(fte_match_set_misc, mask, source_eswitch_owner_vhca_id, clr); 818 spec->outer_second_prio = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_prio, clr); 819 spec->outer_second_cfi = IFC_GET_CLR(fte_match_set_misc, mask, outer_second_cfi, clr); 858 dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec, bool clr) argument 910 dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec, bool clr) argument 955 dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec, bool clr) argument 985 dr_ste_copy_mask_misc4(char *mask, struct mlx5dr_match_misc4 *spec, bool clr) argument 1005 dr_ste_copy_mask_misc5(char *mask, struct mlx5dr_match_misc5 *spec, bool clr) argument 1025 mlx5dr_ste_copy_param(u8 match_criteria, struct mlx5dr_match_param *set_param, struct mlx5dr_match_parameters *mask, bool clr) argument [all...] |
/linux-master/arch/sparc/include/asm/ |
H A D | asmmacro.h | 22 #define RESTORE_ALL b ret_trap_entry; clr %l6;
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H A D | backoff.h | 64 clr tmp; \
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H A D | ns87303.h | 88 unsigned char clr, unsigned char set) 106 value &= ~(reserved[index] | clr); 87 ns87303_modify(unsigned long port, unsigned int index, unsigned char clr, unsigned char set) argument
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_workarounds_types.h | 20 u32 clr; member in struct:i915_wa
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/linux-master/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 45 static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg) argument 47 u32 val = rt_sysc_r32(reg) & ~clr;
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/linux-master/arch/sparc/lib/ |
H A D | ffs.S | 14 clr %o0 21 clr %o1 /* 2 */ 25 1: clr %o2 31 clr %o3 34 clr %o4 40 clr %o5
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H A D | strncmp_64.S | 31 clr %o0
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H A D | ashldi3.S | 24 clr %o5
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H A D | lshrdi3.S | 15 clr %o4
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/linux-master/arch/arm/mach-rpc/ |
H A D | irq.c | 168 unsigned int irq, clr, set; local 181 clr = IRQ_NOREQUEST; 185 clr |= IRQ_NOPROBE; 195 irq_modify_status(irq, clr, set); 203 irq_modify_status(irq, clr, set); 211 irq_modify_status(irq, clr, set); 218 irq_modify_status(irq, clr, set);
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/linux-master/kernel/irq/ |
H A D | devres.c | 236 unsigned int clr; member in struct:irq_generic_chip_devres 244 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); 255 * @clr: IRQ_* bits to clear 264 unsigned int clr, unsigned int set) 273 irq_setup_generic_chip(gc, msk, flags, clr, set); 277 dr->clr = clr; 262 devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set) argument
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/linux-master/drivers/clocksource/ |
H A D | timer-armada-370-xp.c | 88 static void local_timer_ctrl_clrset(u32 clr, u32 set) argument 90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, 173 u32 clr = 0, set = 0; local 178 clr = TIMER0_25MHZ; 179 local_timer_ctrl_clrset(clr, set); 242 u32 clr = 0, set = 0; local 261 clr = TIMER0_25MHZ; 264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); 265 local_timer_ctrl_clrset(clr, set);
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/linux-master/arch/powerpc/include/asm/ |
H A D | dcr-native.h | 112 unsigned clr, unsigned set) 120 val = (mfdcrx(base_data) & ~clr) | set; 124 val = (__mfdcr(base_data) & ~clr) | set; 138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ 140 reg, clr, set) 111 __dcri_clrset(int base_addr, int base_data, int reg, unsigned clr, unsigned set) argument
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H A D | code-patching.h | 94 static inline int modify_instruction(unsigned int *addr, unsigned int clr, argument 97 return patch_instruction(addr, ppc_inst((*addr & ~clr) | set)); 100 static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) argument 102 return modify_instruction((unsigned int *)patch_site_addr(site), clr, set);
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/linux-master/arch/powerpc/include/asm/nohash/32/ |
H A D | pte-8xx.h | 124 unsigned long clr, unsigned long set, int huge); 136 unsigned long clr = ~pte_val(entry) & _PAGE_RO; local 139 pte_update(vma->vm_mm, address, ptep, clr, set, huge); 189 unsigned long clr, unsigned long set, int huge) 193 pte_basic_t new = (old & ~(pte_basic_t)clr) | set; 188 pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p, unsigned long clr, unsigned long set, int huge) argument
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H A D | hugetlb-8xx.h | 63 unsigned long clr = ~pte_val(pte_wrprotect(__pte(~0))); local 66 pte_update(mm, addr, ptep, clr, set, 1);
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/linux-master/arch/m68k/math-emu/ |
H A D | fp_util.S | 70 2: clr.l %d0 99 clr.l %d1 | sign defaults to zero 109 clr.l (%a0) 116 clr.l (%a0)+ 117 clr.l (%a0)+ 118 clr.l (%a0) 142 clr.l (%a0) | low lword = 0 236 clr.b (%a0) 274 clr.l %d0 279 clr [all...] |
/linux-master/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_wow.c | 127 u32 set, clr; local 160 clr = AR_WOW_LENGTH1_MASK(pattern_count); 161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); 165 clr = AR_WOW_LENGTH2_MASK(pattern_count); 166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); 170 clr = AR_WOW_LENGTH3_MASK(pattern_count); 171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); 175 clr = AR_WOW_LENGTH4_MASK(pattern_count); 176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr);
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/linux-master/arch/mips/pic32/pic32mzda/ |
H A D | config.c | 71 u32 clr, set; local 73 clr = (0x3ff << 4) | (0x3ff << 16); 75 return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set);
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/linux-master/drivers/staging/media/omap4iss/ |
H A D | iss.h | 187 * @clr: bit mask to be cleared 191 u32 offset, u32 clr) 195 iss_reg_write(iss, res, offset, v & ~clr); 219 * @clr: bit mask to be cleared 222 * Clear the clr mask first and then set the set mask. 226 u32 offset, u32 clr, u32 set) 230 iss_reg_write(iss, res, offset, (v & ~clr) | set); 190 iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res, u32 offset, u32 clr) argument 225 iss_reg_update(struct iss_device *iss, enum iss_mem_resources res, u32 offset, u32 clr, u32 set) argument
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/linux-master/arch/mips/kernel/ |
H A D | head.S | 35 .macro setup_c0_status set clr 38 or t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr 39 xor t0, 0x1f|\clr
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/linux-master/arch/powerpc/include/asm/book3s/64/ |
H A D | radix.h | 154 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, argument 166 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) 174 pte_t *ptep, unsigned long clr, 180 old_pte = __radix_pte_update(ptep, clr, set); 286 pmd_t *pmdp, unsigned long clr, 289 pud_t *pudp, unsigned long clr, 172 radix__pte_update(struct mm_struct *mm, unsigned long addr, pte_t *ptep, unsigned long clr, unsigned long set, int huge) argument
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