/haiku/headers/private/kernel/boot/ |
H A D | uart.h | 17 int64 clock; member in struct:__anon9
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/haiku/src/system/kernel/arch/arm/ |
H A D | arch_uart_8250_omap.cpp | 17 ArchUART8250Omap::ArchUART8250Omap(addr_t base, int64 clock) argument 19 DebugUART8250(base, clock) 62 arch_get_uart_8250_omap(addr_t base, int64 clock) argument 65 ArchUART8250Omap* uart = new(buffer) ArchUART8250Omap(base, clock);
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H A D | arch_debug_console.cpp | 111 args->arch_args.uart.clock); 115 args->arch_args.uart.clock); 119 args->arch_args.uart.clock);
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H A D | arch_uart_pl011.cpp | 149 ArchUARTPL011::ArchUARTPL011(addr_t base, int64 clock) argument 151 DebugUART(base, clock) 327 arch_get_uart_pl011(addr_t base, int64 clock) argument 330 ArchUARTPL011 *uart = new(buffer) ArchUARTPL011(base, clock);
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/haiku/headers/private/kernel/arch/generic/ |
H A D | debug_uart_8250.h | 25 DebugUART8250(addr_t base, int64 clock); 40 DebugUART8250* arch_get_uart_8250(addr_t base, int64 clock);
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H A D | debug_uart.h | 19 DebugUART(addr_t base, int64 clock) argument 21 fClock(clock),
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/haiku/headers/private/kernel/arch/arm/ |
H A D | arch_uart_pl011.h | 24 ArchUARTPL011(addr_t base, int64 clock); 46 ArchUARTPL011 *arch_get_uart_pl011(addr_t base, int64 clock);
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H A D | arch_uart_8250_omap.h | 25 ArchUART8250Omap(addr_t base, int64 clock); 35 DebugUART8250* arch_get_uart_8250_omap(addr_t base, int64 clock);
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/haiku/src/system/kernel/arch/riscv64/ |
H A D | arch_uart_sifive.cpp | 11 ArchUARTSifive::ArchUARTSifive(addr_t base, int64 clock) argument 13 DebugUART(base, clock) 112 arch_get_uart_sifive(addr_t base, int64 clock) argument 115 ArchUARTSifive* uart = new(buffer) ArchUARTSifive(base, clock);
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H A D | arch_debug_console.cpp | 109 args->arch_args.uart.clock); 113 args->arch_args.uart.clock);
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H A D | arch_system_info.cpp | 51 #warning IMPLEMENT arch_system_info_init clock frequency
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/haiku/src/system/boot/platform/efi/arch/arm64/ |
H A D | arch_acpi.cpp | 23 uart.clock != 0 ? uart.clock : 0x16e3600); 43 uart.clock = spcr->clock; 49 dprintf("discovered uart from acpi: base=%lx, irq=%u, clock=%lu\n", 50 uart.regs.start, uart.irq, uart.clock);
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/haiku/src/add-ons/accelerants/intel_extreme/ |
H A D | pll.h | 50 void hsw_ddi_calculate_wrpll(int clock /* in Hz */, 52 bool skl_ddi_calculate_wrpll(int clock /* in Hz */,
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/haiku/headers/private/graphics/common/ |
H A D | i2c.h | 18 int low; // low period of clock (4.7/1.3) 19 int high; // high period of clock (4.0/0.6) 23 int r; // maximum raise time of clock and data signal (1.0/0.3) 24 int f; // maximum fall time of clock and data signal (0.3/0.3) 27 // clock stretching limits, not part of i2c standard 41 typedef status_t (*i2c_set_signals)(void *cookie, int clock, int data); 43 typedef status_t (*i2c_get_signals)(void *cookie, int *clock, int *data);
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/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_i2c.c | 73 static int i2c_set_lines(int clock,int data) argument 81 (clock ? 0 : I2C_CLOCK)| 86 (clock ? I2C_CLOCK : 0); 95 /*loop until the clock is as required*/ 102 LOG(8,("I2C: Timeout on set lines - clock:%d data:%d actual:%x\n",clock,data,DXIR(GENIODATA))); 113 int clock; local 118 /*read the data and clock lines*/ 120 clock = (data&I2C_CLOCK) ? 1 : 0; 133 }while (!clock); /*wai [all...] |
/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | i2c.c | 19 int i2c_set_lines(int clock, int data); 84 int i2c_set_lines(int clock,int data) argument 92 (clock ? 0 : I2C_CLOCK)| 97 (clock ? I2C_CLOCK : 0); 106 /*loop until the clock is as required*/ 113 // LOG(8,("I2C: Timeout on set lines - clock:%d data:%d actual:%x\n",clock,data,DXIR(GENIODATA))); 124 int clock; local 129 /*read the data and clock lines*/ 131 clock [all...] |
/haiku/src/add-ons/accelerants/via/engine/ |
H A D | i2c.c | 19 int i2c_set_lines(int clock, int data); 84 int i2c_set_lines(int clock,int data) argument 92 (clock ? 0 : I2C_CLOCK)| 97 (clock ? I2C_CLOCK : 0); 106 /*loop until the clock is as required*/ 113 // LOG(8,("I2C: Timeout on set lines - clock:%d data:%d actual:%x\n",clock,data,DXIR(GENIODATA))); 124 int clock; local 129 /*read the data and clock lines*/ 131 clock [all...] |
/haiku/src/system/kernel/arch/arm64/ |
H A D | arch_debug_console.cpp | 104 args->arch_args.uart.clock); 108 args->arch_args.uart.clock); 112 args->arch_args.uart.clock); 116 args->arch_args.uart.clock);
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H A D | arch_uart_linflex.cpp | 19 ArchUARTlinflex::ArchUARTlinflex(addr_t base, int64 clock) argument 21 DebugUART(base, clock) 195 arch_get_uart_linflex(addr_t base, int64 clock) argument 198 ArchUARTlinflex *uart = new(buffer) ArchUARTlinflex(base, clock);
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/haiku/src/system/kernel/arch/generic/ |
H A D | debug_uart_8250.cpp | 30 DebugUART8250::DebugUART8250(addr_t base, int64 clock) argument 32 DebugUART(base, clock) 181 arch_get_uart_8250(addr_t base, int64 clock) argument 184 DebugUART8250* uart = new(buffer) DebugUART8250(base, clock);
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/haiku/headers/private/kernel/arch/riscv64/ |
H A D | arch_uart_sifive.h | 71 ArchUARTSifive(addr_t base, int64 clock); 102 ArchUARTSifive* arch_get_uart_sifive(addr_t base, int64 clock);
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/haiku/src/add-ons/accelerants/radeon_hd/ |
H A D | pll.h | 49 /* pixel clock to be programmed (kHz)*/ 52 /* flags for the current clock */ 99 /* pixel clock to be used in pll calculations (kHz) */ 105 status_t pll_set_external(uint32 clock); 106 status_t pll_set_dce(uint32 clock, uint8 clockType, uint8 clockSource);
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/haiku/src/add-ons/media/media-add-ons/radeon/ |
H A D | Theater100.h | 56 void SetClock(theater_standard standard, radeon_video_clock clock);
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/haiku/src/add-ons/kernel/drivers/audio/ice1712/ |
H A D | ice1712.h | 81 uint8 clock; member in struct:_codecCommLines 102 uint8 clock; //an index member in struct:ice1712Settings 182 #define DELTA66_CLK 0x20 // clock 188 #define AP2496_CLK 0x02 // clock 196 #define DELTA1010LT_CLK 0x02 // clock 207 #define VX442_CLK 0x02 // clock
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/haiku/src/add-ons/kernel/drivers/audio/ac97/ |
H A D | ac97.c | 254 dev->clock = 48000; /* default clock on non-broken motherboards */ 439 value = (uint32)((rate * 48000ULL) / dev->clock); /* need 64 bit calculation for rates 96000 or higher */ 441 LOG(("ac97_set_rate: clock = %" B_PRIu32 ", " 444 dev->clock, rate, value)); 481 *rate = (uint32)((value * (uint64)dev->clock) / 48000); /* need 64 bit calculation to avoid overflow*/ 487 ac97_set_clock(ac97_dev *dev, uint32 clock) argument 489 LOG(("ac97_set_clock: clock = %" B_PRIu32 "\n", clock)); 490 dev->clock [all...] |