Searched refs:clks (Results 1 - 25 of 653) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-bulk.c16 struct clk_bulk_data *clks)
22 clks[i].id = NULL;
23 clks[i].clk = NULL;
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id);
28 clks[i].clk = of_clk_get(np, i);
29 if (IS_ERR(clks[i].clk)) {
30 ret = PTR_ERR(clks[i].clk);
33 clks[i].clk = NULL;
41 clk_bulk_put(i, clks);
47 struct clk_bulk_data **clks)
15 of_clk_bulk_get(struct device_node *np, int num_clks, struct clk_bulk_data *clks) argument
46 of_clk_bulk_get_all(struct device_node *np, struct clk_bulk_data **clks) argument
72 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) argument
81 __clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks, bool optional) argument
114 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
121 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
128 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) argument
139 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) argument
161 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) argument
176 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) argument
211 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) argument
227 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) argument
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H A Dclk-devres.c103 struct clk_bulk_data *clks; member in struct:clk_bulk_devres
111 clk_bulk_put(devres->num_clks, devres->clks);
115 struct clk_bulk_data *clks, bool optional)
126 ret = clk_bulk_get_optional(dev, num_clks, clks);
128 ret = clk_bulk_get(dev, num_clks, clks);
130 devres->clks = clks;
141 struct clk_bulk_data *clks)
143 return __devm_clk_bulk_get(dev, num_clks, clks, false);
148 struct clk_bulk_data *clks)
114 __devm_clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks, bool optional) argument
140 devm_clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
147 devm_clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
161 devm_clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) argument
193 devm_clk_bulk_get_all_enable(struct device *dev, struct clk_bulk_data **clks) argument
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/linux-master/drivers/clk/mmp/
H A Dclk.c21 unit->clk_data.clks = clk_table;
27 struct mmp_param_fixed_rate_clk *clks,
34 clk = clk_register_fixed_rate(NULL, clks[i].name,
35 clks[i].parent_name,
36 clks[i].flags,
37 clks[i].fixed_rate);
40 __func__, clks[i].name);
43 if (clks[i].id)
44 unit->clk_table[clks[i].id] = clk;
49 struct mmp_param_fixed_factor_clk *clks,
26 mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_rate_clk *clks, int size) argument
48 mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit, struct mmp_param_fixed_factor_clk *clks, int size) argument
70 mmp_register_general_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_general_gate_clk *clks, void __iomem *base, int size) argument
96 mmp_register_gate_clks(struct mmp_clk_unit *unit, struct mmp_param_gate_clk *clks, void __iomem *base, int size) argument
124 mmp_register_mux_clks(struct mmp_clk_unit *unit, struct mmp_param_mux_clk *clks, void __iomem *base, int size) argument
152 mmp_register_div_clks(struct mmp_clk_unit *unit, struct mmp_param_div_clk *clks, void __iomem *base, int size) argument
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H A Dclk-pll.c142 struct mmp_param_pll_clk *clks,
151 if (clks[i].offset)
152 reg = base + clks[i].offset;
154 clk = mmp_clk_register_pll(clks[i].name,
155 clks[i].default_rate,
156 base + clks[i].enable_offset,
157 clks[i].enable,
158 reg, clks[i].shift,
159 clks[i].input_rate,
160 base + clks[
141 mmp_register_pll_clks(struct mmp_clk_unit *unit, struct mmp_param_pll_clk *clks, void __iomem *base, int size) argument
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/linux-master/drivers/clk/imx/
H A Dclk-imx8ulp.c149 struct clk_hw **clks; local
158 clks = clk_data->hws;
160 clks[IMX8ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
167 clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
168 clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
170 clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base + 0x500);
171 clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x600);
172 clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6);
174 clks[IMX8ULP_CLK_SPLL3_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd0", "spll3_vcodiv", base + 0x614, 0);
175 clks[IMX8ULP_CLK_SPLL3_PFD
233 struct clk_hw **clks; local
315 struct clk_hw **clks; local
398 struct clk_hw **clks; local
453 struct clk_hw **clks; local
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/linux-master/drivers/clk/mxs/
H A Dclk-imx28.c145 static struct clk *clks[clk_max]; variable in typeref:struct:clk
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
175 clks[ref_pi
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H A Dclk-imx23.c90 static struct clk *clks[clk_max]; variable in typeref:struct:clk
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
120 clks[gpmi_se
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/linux-master/drivers/clk/hisilicon/
H A Dclk.c51 clk_data->clk_data.clks = clk_table;
80 clk_data->clk_data.clks = clk_table;
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name,
99 clks[i].parent_name,
100 clks[i].flags,
101 clks[i].fixed_rate);
104 __func__, clks[i].name);
107 data->clk_data.clks[clks[
120 hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, int nums, struct hisi_clock_data *data) argument
150 hisi_clk_register_mux(const struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) argument
188 hisi_clk_register_phase(struct device *dev, const struct hisi_phase_clock *clks, int nums, struct hisi_clock_data *data) argument
212 hisi_clk_register_divider(const struct hisi_divider_clock *clks, int nums, struct hisi_clock_data *data) argument
250 hisi_clk_register_gate(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) argument
287 hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, int nums, struct hisi_clock_data *data) argument
316 hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, int nums, struct hisi_clock_data *data) argument
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H A Dclk-hisi-phase.c94 const struct hisi_phase_clock *clks,
104 init.name = clks->name;
106 init.flags = clks->flags;
107 init.parent_names = clks->parent_names ? &clks->parent_names : NULL;
108 init.num_parents = clks->parent_names ? 1 : 0;
110 phase->reg = base + clks->offset;
111 phase->shift = clks->shift;
112 phase->mask = (BIT(clks->width) - 1) << clks
93 clk_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks, void __iomem *base, spinlock_t *lock) argument
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/linux-master/include/linux/platform_data/x86/
H A Dclk-pmc-atom.h29 * @clks: pointer to set of registered clocks, typically 0..5
35 const struct pmc_clk *clks; member in struct:pmc_clk_data
/linux-master/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable in typeref:struct:clk
403 for (i = 0; i < ARRAY_SIZE(clks); i++)
404 clks[i] = ERR_PTR(-ENODEV);
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1);
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]);
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq);
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]);
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]);
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed(
681 clks[clks_idx_in
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/linux-master/drivers/clk/socfpga/
H A Dclk-gate-s10.c127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) argument
132 const char *parent_name = clks->parent_name;
139 socfpga_clk->hw.reg = regbase + clks->gate_reg;
140 socfpga_clk->hw.bit_idx = clks->gate_idx;
145 socfpga_clk->fixed_div = clks->fixed_div;
147 if (clks->div_reg)
148 socfpga_clk->div_reg = regbase + clks->div_reg;
152 socfpga_clk->width = clks->div_width;
153 socfpga_clk->shift = clks->div_offset;
155 if (clks
185 agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) argument
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H A Dstratix10-clk.h76 struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
78 struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
80 struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
82 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
84 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
86 struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
88 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
90 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
H A Dclk-periph-s10.c101 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, argument
107 const char *name = clks->name;
108 const char *parent_name = clks->parent_name;
115 periph_clk->hw.reg = reg + clks->offset;
119 init.flags = clks->flags;
121 init.num_parents = clks->num_parents;
124 init.parent_data = clks->parent_data;
137 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, argument
143 const char *name = clks->name;
144 const char *parent_name = clks
172 s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks, void __iomem *regbase) argument
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/linux-master/drivers/clk/mediatek/
H A Dclk-cpumux.h15 const struct mtk_composite *clks, int num,
18 void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
/linux-master/drivers/clk/axis/
H A Dclk-artpec6.c43 struct clk **clks; local
56 clks = clkdata->clk_table;
59 clks[i] = ERR_PTR(-EPROBE_DEFER);
85 clks[ARTPEC6_CLK_CPU] =
88 clks[ARTPEC6_CLK_CPU_PERIPH] =
92 clks[ARTPEC6_CLK_UART_PCLK] =
94 clks[ARTPEC6_CLK_UART_REFCLK] =
98 clks[ARTPEC6_CLK_SPI_PCLK] =
100 clks[ARTPEC6_CLK_SPI_SSPCLK] =
104 clks[ARTPEC6_CLK_DBG_PCL
121 struct clk **clks = clkdata->clk_table; local
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/linux-master/sound/soc/sof/imx/
H A Dimx-common.c77 int imx8_parse_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) argument
81 ret = devm_clk_bulk_get(sdev->dev, clks->num_dsp_clks, clks->dsp_clks);
89 int imx8_enable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) argument
91 return clk_bulk_prepare_enable(clks->num_dsp_clks, clks->dsp_clks);
95 void imx8_disable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks) argument
97 clk_bulk_disable_unprepare(clks->num_dsp_clks, clks->dsp_clks);
H A Dimx-common.h23 int imx8_parse_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks);
24 int imx8_enable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks);
25 void imx8_disable_clocks(struct snd_sof_dev *sdev, struct imx_clocks *clks);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
237 if (clk_mgr_base->clks.dispclk_khz == 0 ||
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks
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/linux-master/include/linux/
H A Dclk.h84 * a convenience to consumers which require multiple clks. This
182 * Returns false otherwise. Note that two NULL clks are treated as matching.
309 const struct clk_bulk_data *clks);
335 clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks) argument
358 void clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks);
365 const struct clk_bulk_data *clks)
393 * @clks: the clk_bulk_data table of consumer
396 * operation. If any of the clk cannot be acquired then any clks
410 struct clk_bulk_data *clks);
415 * @clks
364 clk_bulk_unprepare(int num_clks, const struct clk_bulk_data *clks) argument
932 clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
938 clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
944 clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) argument
985 devm_clk_bulk_get(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
991 devm_clk_bulk_get_optional(struct device *dev, int num_clks, struct clk_bulk_data *clks) argument
997 devm_clk_bulk_get_all(struct device *dev, struct clk_bulk_data **clks) argument
1004 devm_clk_bulk_get_all_enable(struct device *dev, struct clk_bulk_data **clks) argument
1018 clk_bulk_put(int num_clks, struct clk_bulk_data *clks) argument
1020 clk_bulk_put_all(int num_clks, struct clk_bulk_data *clks) argument
1029 clk_bulk_enable(int num_clks, const struct clk_bulk_data *clks) argument
1038 clk_bulk_disable(int num_clks, const struct clk_bulk_data *clks) argument
1129 clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks) argument
1143 clk_bulk_disable_unprepare(int num_clks, const struct clk_bulk_data *clks) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
78 clk_mgr->clks.p_state_change_support = true;
79 clk_mgr->clks.prev_p_state_change_support = true;
80 clk_mgr->clks.max_supported_dppclk_khz = 1200000;
81 clk_mgr->clks.max_supported_dispclk_khz = 1200000;
101 if (clk_mgr_base->clks.dispclk_khz == 0 ||
110 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz))
111 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
117 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz))
118 clk_mgr_base->clks
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c37 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
43 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
45 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
75 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
120 * , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) ||
121 * new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz)
142 * for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we
144 * for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz,
146 * new_clocks->dispclk_khz and clk_mgr_base->clks
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/linux-master/drivers/clk/sunxi/
H A Dclk-a10-pll2.c42 struct clk **clks, *base_clk, *prediv_clk; local
57 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
58 if (!clks)
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
127 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
141 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
150 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
155 clks[SUN4I_A10_PLL2_8
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/linux-master/drivers/clk/zynq/
H A Dclkc.c62 static struct clk *clks[clk_max]; variable in typeref:struct:clk
147 clks[fclk] = clk_register_gate(NULL, clk_name,
152 if (clk_prepare_enable(clks[fclk]))
171 clks[fclk] = ERR_PTR(-ENOMEM);
197 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
200 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
209 clks[clk0] = ERR_PTR(-ENOMEM);
211 clks[clk1] = ERR_PTR(-ENOMEM);
260 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
266 clks[ddrpl
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/linux-master/drivers/clk/microchip/
H A Dclk-pic32mzda.c128 struct clk *clks[MAXCLKS]; member in struct:pic32mzda_clk_data
157 struct clk **clks; local
173 clks = &cd->clks[0];
176 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
178 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
180 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
182 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
184 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
189 clks[SOSCCL
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