Searched refs:clk_pol (Results 1 - 16 of 16) sorted by path

/linux-master/drivers/media/dvb-frontends/
H A Dstv0367.h27 int clk_pol; member in struct:stv0367_config
H A Dlgs8gxx.c518 u8 serial, u8 clk_pol, u8 clk_gated)
530 t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL;
517 lgs8gxx_set_mpeg_mode(struct lgs8gxx_state *priv, u8 serial, u8 clk_pol, u8 clk_gated) argument
H A Dmxl692_defs.h462 u8 clk_pol; member in struct:MXL_EAGLE_OOB_DEMOD_PARAMS_T
H A Dstv0367.c968 stv0367ter_set_clk_pol(state, state->config->clk_pol);
2277 switch (state->config->clk_pol) {
/linux-master/include/media/i2c/
H A Dmt9v032.h6 unsigned int clk_pol:1; member in struct:mt9v032_platform_data
/linux-master/drivers/gpu/drm/imx/ipuv3/
H A Dipuv3-crtc.c299 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
/linux-master/drivers/gpu/drm/imx/lcdc/
H A Dimx-lcdc.c203 const int clk_pol = local
220 FIELD_PREP(IMX21LCDC_LPCR_CLKPOL, clk_pol),
/linux-master/drivers/gpu/ipu-v3/
H A Dipu-di.c617 if (sig->clk_pol)
/linux-master/drivers/media/i2c/
H A Dmt9v032.c333 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
1038 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
/linux-master/drivers/media/pci/cx23885/
H A Dcx23885-dvb.c839 .clk_pol = 0,
846 .clk_pol = 0,
/linux-master/drivers/media/pci/ddbridge/
H A Dddbridge-core.c929 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
936 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
/linux-master/drivers/media/pci/ngene/
H A Dngene-cards.c368 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
375 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
/linux-master/drivers/media/platform/st/sti/c8sectpfe/
H A Dc8sectpfe-dvb.c81 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
88 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
95 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
/linux-master/drivers/media/platform/ti/omap3isp/
H A Disp.c443 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
2067 buscfg->bus.parallel.clk_pol =
H A Domap3isp.h31 * @clk_pol: Pixel clock polarity
45 unsigned int clk_pol:1; member in struct:isp_parallel_cfg
/linux-master/include/video/
H A Dimx-ipu-v3.h39 unsigned clk_pol:1; /* true = rising edge */ member in struct:ipu_di_signal_cfg

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