Searched refs:c7 (Results 1 - 25 of 64) sorted by relevance

123

/linux-master/arch/arm/mm/
H A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
143 mcr p15, 0, r0, c7, c1
[all...]
H A Dcache-v4.S40 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
59 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
115 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
69 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
97 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-mohawk.S62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
117 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-arm920.S77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
158 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-fa526.S58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c
[all...]
H A Dproc-arm946.S57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
59 mcr p15, 0, ip, c7, c10, 4 @ drain WB
73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
137 mcr p15, 0, r0, c7, c
[all...]
H A Dtlb-fa.S40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
60 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
61 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm922.S79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
160 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm1020.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
145 mcr p15, 0, ip, c7, c10, 4 @ drain WB
153 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-arm1020e.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 mcr p15, 0, ip, c7, c10, 4 @ drain WB
144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
154 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-arm926.S69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
138 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-arm1026.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
148 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
168 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm1022.S85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
86 mcr p15, 0, ip, c7, c10, 4 @ drain WB
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c1
[all...]
H A Dproc-arm925.S109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 mcr p15, 0, ip, c7, c10, 4 @ drain WB
112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
175 mcrne p15, 0, ip, c7, c
[all...]
H A Dcache-v4wt.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-xsc3.S68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
174 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c
[all...]
H A Dcache-v4wb.S58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
94 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
116 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
117 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
122 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
163 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
164 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
169 mcr p15, 0, r0, c7, c
[all...]
H A Dtlb-v6.S39 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
57 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
70 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
85 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-arm940.S50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
52 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
120 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
162 2: mcr p15, 0, r3, c7, c1
[all...]
H A Dproc-feroceon.S73 mcr p15, 0, r0, c7, c10, 4 @ drain WB
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
96 mcr p15, 0, ip, c7, c10, 4 @ drain WB
98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
116 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
161 mcrne p15, 0, ip, c7, c
[all...]
H A Dproc-sa110.S65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
66 mcr p15, 0, ip, c7, c10, 4 @ drain WB
68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
155 mcr p15, 0, r0, c7, c10, 4 @ drain WB
162 mcr p15, 0, r10, c7, c7
[all...]
H A Dproc-arm720.S66 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
136 mcr p15, 0, r0, c7, c
[all...]
/linux-master/arch/arm/include/asm/vdso/
H A Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/linux-master/arch/arm/boot/compressed/
H A Dhead-xscale.S27 mcr p15, 0, r0, c7, c10, 4 @ drain WB
28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches

Completed in 216 milliseconds

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