/linux-master/arch/arm/mm/ |
H A D | pabort-v7.S | 20 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
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H A D | pabort-v6.S | 20 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
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H A D | abort-ev7.S | 18 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | cache-v4wt.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
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H A D | cache-fa.S | 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 134 mcr p15, 0, r0, c7, c5, [all...] |
H A D | abort-ev4.S | 20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | abort-ev4t.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | cache-v6.S | 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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H A D | proc-arm946.S | 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 328 mcr p15, 0, r0, c7, c5, [all...] |
H A D | tlb-v6.S | 50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
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H A D | tlb-v4wb.S | 38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
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H A D | tlb-v4wbi.S | 40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
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H A D | abort-ev5tj.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | abort-ev5t.S | 21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | proc-fa526.S | 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush 142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM 148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All 150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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H A D | proc-xsc3.S | 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 252 mcr p15, 0, r0, c7, c5, [all...] |
H A D | proc-arm940.S | 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 281 mcr p15, 0, r0, c6, c5, 0 287 mcr p15, 0, r0, c6, c5, 1 319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access 320 mcr p15, 0, r0, c5, c0, 1
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H A D | proc-mohawk.S | 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 361 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
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H A D | abort-ev6.S | 22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
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H A D | cache-v4wb.S | 58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/volt/ |
H A D | gk20a.h | 32 int c5; member in struct:cvb_coef
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/linux-master/arch/arm/include/asm/vdso/ |
H A D | cp15.h | 29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6) 30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
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/linux-master/arch/arm/include/asm/hardware/ |
H A D | cp14.h | 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) 62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4) 78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5) 94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6) 110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7) 127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1) 142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4) 152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) 167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4) 183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, [all...] |
/linux-master/tools/testing/selftests/net/ |
H A D | route_localnet.sh | 44 ping -c5 -I veth0 127.25.3.14 61 ping -c5 -I veth0 127.25.3.14
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/linux-master/tools/perf/arch/s390/include/ |
H A D | dwarf-regs-table.h | 35 REG_DWARFNUM_NAME(c5, 37),
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