Searched refs:c5 (Results 1 - 25 of 60) sorted by relevance

123

/linux-master/arch/arm/mm/
H A Dpabort-v7.S20 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
H A Dpabort-v6.S20 mrc p15, 0, r1, c5, c0, 1 @ get IFSR
H A Dabort-ev7.S18 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dcache-v4wt.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
H A Dcache-fa.S44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
70 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
98 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
134 mcr p15, 0, r0, c7, c5,
[all...]
H A Dabort-ev4.S20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dabort-ev4t.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dcache-v6.S42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
H A Dproc-arm946.S57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
328 mcr p15, 0, r0, c7, c5,
[all...]
H A Dtlb-v6.S50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
86 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A Dtlb-v4wb.S38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
H A Dtlb-v4wbi.S40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
H A Dabort-ev5tj.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dabort-ev5t.S21 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dproc-fa526.S108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
111 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
150 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
H A Dproc-xsc3.S149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
204 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
231 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
252 mcr p15, 0, r0, c7, c5,
[all...]
H A Dproc-arm940.S50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
275 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c6, c5, 0
287 mcr p15, 0, r0, c6, c5, 1
319 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
320 mcr p15, 0, r0, c5, c0, 1
H A Dproc-mohawk.S92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
202 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
318 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
361 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
H A Dabort-ev6.S22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
H A Dcache-v4wb.S58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dgk20a.h32 int c5; member in struct:cvb_coef
/linux-master/arch/arm/include/asm/vdso/
H A Dcp15.h29 #define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
30 #define ICIALLU __ACCESS_CP15(c7, 0, c5, 0)
/linux-master/arch/arm/include/asm/hardware/
H A Dcp14.h47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
62 #define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
78 #define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
94 #define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
110 #define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
127 #define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
142 #define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
167 #define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
183 #define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5,
[all...]
/linux-master/tools/testing/selftests/net/
H A Droute_localnet.sh44 ping -c5 -I veth0 127.25.3.14
61 ping -c5 -I veth0 127.25.3.14
/linux-master/tools/perf/arch/s390/include/
H A Ddwarf-regs-table.h35 REG_DWARFNUM_NAME(c5, 37),

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