Searched refs:bit_group_1 (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gt/
H A Dgen8_engine_cs.h54 u32 bit_group_1, u32 offset)
59 batch[1] = bit_group_1;
66 u32 bit_group_1, u32 offset)
68 return __gen8_emit_pipe_control(batch, 0, bit_group_1, offset);
72 u32 bit_group_1, u32 offset)
75 bit_group_1, offset);
53 __gen8_emit_pipe_control(u32 *batch, u32 bit_group_0, u32 bit_group_1, u32 offset) argument
65 gen8_emit_pipe_control(u32 *batch, u32 bit_group_1, u32 offset) argument
71 gen12_emit_pipe_control(u32 *batch, u32 bit_group_0, u32 bit_group_1, u32 offset) argument
H A Dgen8_engine_cs.c257 u32 bit_group_1 = 0; local
283 bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
285 bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
286 bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
287 bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
289 bit_group_1 |= PIPE_CONTROL_DEPTH_STALL;
290 bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE;
291 bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE;
293 bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX;
294 bit_group_1 |
[all...]
/linux-master/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c118 emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value) argument
121 dw[i++] = bit_group_1;

Completed in 121 milliseconds