Searched refs:bank_reg (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpio/
H A Dgpio-aspeed-sgpio.c104 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, function
180 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
199 addr_r = bank_reg(gpio, bank, reg_rdata);
200 addr_w = bank_reg(gpio, bank, reg_val);
279 status_addr = bank_reg(gpio, bank, reg_irq_status);
298 addr = bank_reg(gpio, bank, reg_irq_enable);
371 addr = bank_reg(gpio, bank, reg_irq_type0);
376 addr = bank_reg(gpio, bank, reg_irq_type1);
381 addr = bank_reg(gpio, bank, reg_irq_type2);
406 reg = ioread32(bank_reg(dat
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H A Dgpio-npcm-sgpio.c137 static void __iomem *bank_reg(struct npcm_sgpio *gpio, function
236 addr = bank_reg(gpio, bank, WRITE_DATA);
256 addr = bank_reg(gpio, bank, WRITE_DATA);
260 addr = bank_reg(gpio, bank, READ_DATA);
328 addr = bank_reg(gpio, bank, EVENT_CFG);
346 addr = bank_reg(gpio, bank, EVENT_STS);
364 status_addr = bank_reg(gpio, bank, EVENT_STS);
418 addr = bank_reg(gpio, bank, EVENT_CFG);
445 reg = ioread8(bank_reg(gpio, bank, EVENT_STS));
484 iowrite16(0, bank_reg(gpi
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H A Dgpio-aspeed.c210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, function
311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
399 addr = bank_reg(gpio, bank, reg_val);
432 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
460 void __iomem *addr = bank_reg(gpio, bank, reg_dir);
499 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
542 status_addr = bank_reg(gpi
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/linux-master/drivers/i2c/
H A Di2c-stub.c46 static u8 bank_reg[MAX_CHIPS]; variable
47 module_param_array(bank_reg, byte, NULL, S_IRUGO);
48 MODULE_PARM_DESC(bank_reg, "Bank register");
76 u8 bank_reg; member in struct:stub_chip
176 if (chip->bank_words && command == chip->bank_reg) {
320 chip->bank_reg = bank_reg[i];
/linux-master/drivers/clk/qcom/
H A Dclk-rcg.h104 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
114 u32 bank_reg; member in struct:clk_dyn_rcg
H A Dclk-rcg.c73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
H A Dgcc-ipq806x.c2423 .bank_reg = 0x3ca0,
2495 .bank_reg = 0x3ca0,
2567 .bank_reg = 0x3ce0,
2639 .bank_reg = 0x3d00,
2715 .bank_reg = 0x3dc0,
2785 .bank_reg = 0x3d20,
2838 .bank_reg = 0x3d40,
2895 .bank_reg = 0x36C0,
2955 .bank_reg = 0x3d80,
3015 .bank_reg
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H A Dmmcc-msm8960.c832 .bank_reg = 0x0060,
894 .bank_reg = 0x0074,
997 .bank_reg = 0x0080,
1077 .bank_reg = 0x0178,
1292 .bank_reg = 0x00c0,
1405 .bank_reg = 0x00e8,
1645 .bank_reg = 0x00f8,

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