Searched refs:ast_set_index_reg_mask (Results 1 - 6 of 6) sorted by relevance
/linux-master/drivers/gpu/drm/ast/ |
H A D | ast_dp.c | 40 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 47 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE4, 106 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 112 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 156 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE5, 174 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); 186 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); 270 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE0, ASTDP_AND_CLEAR_MASK, 272 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); 273 ast_set_index_reg_mask(as [all...] |
H A D | ast_mode.c | 305 ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, stdtable->seq[0]); 312 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00); 349 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00); 354 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x00, 0x00, temp); 359 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x01, 0x00, temp); 364 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x02, 0x00, temp); 371 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x03, 0xE0, (temp & 0x1f)); 376 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x04, 0x00, temp); 381 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); 383 ast_set_index_reg_mask(as [all...] |
H A D | ast_dp501.c | 36 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 44 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); 81 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x40); 86 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, ~0x40, 0x00); 113 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data); 135 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, data); 169 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9a, 0x00, 0x00); 416 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); 445 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00);
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H A D | ast_i2c.c | 38 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf1, ujcrb7); 54 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0xf4, ujcrb7);
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H A D | ast_drv.h | 367 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index, function
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H A D | ast_post.c | 61 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info); 70 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01); 71 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00); 77 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg); 366 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */
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