/linux-master/arch/alpha/lib/ |
H A D | strlen.S | 41 and $2, $3, $2 43 and $2, 0x0f, $1 47 and $2, 0x33, $1 51 and $2, 0x55, $1
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H A D | strcat.S | 37 and $2, $3, $2 39 and $2, 0xf0, $3 # binary search for that set bit 40 and $2, 0xcc, $4 41 and $2, 0xaa, $5
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H A D | strncat.S | 11 * implementation in lib/string.c and is, IMHO, more sensible. 42 and $2, $3, $2 44 and $2, 0xf0, $3 # binary search for that set bit 45 and $2, 0xcc, $4 46 and $2, 0xaa, $5 68 and $24, 0x80, $2 # no zero next byte 77 1: /* Here we must read the next DST word and clear the first byte. */
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H A D | dbg_current.S | 23 and $1, $2, $3
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H A D | dbg_stackkill.S | 25 and $30, $2, $2
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H A D | memset.S | 5 * This is an efficient (and small) implementation of the C library "memset()" 10 * This routine is "moral-ware": you are free to use it any way you wish, and 14 * The scheduling comments are according to the EV5 documentation (and done by 33 and $17,255,$1 /* E1 */ 52 and $16,7,$3 /* E0 */ 61 mskql $4,$16,$4 /* .. E1 (and possible load stall) */ 73 and $18,7,$18 /* .. E1 */ 88 mskqh $7,$6,$2 /* .. E1 (and load stall) */
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H A D | memmove.S | 34 and $2,7,$2 /* Test for src/dest co-alignment. */ 35 and $16,7,$1 39 and $4,7,$1 58 and $4,7,$6 129 and $4,7,$6
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/linux-master/arch/sparc/lib/ |
H A D | fls64.S | 5 * and onward. 17 and %o0, %g2, %g2 25 and %o0, %g2, %g2 33 and %o0, %g2, %g2 40 and %o0, %g2, %g2 47 and %o0, %g2, %g2 55 and %o0, %g3, %o0
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H A D | strncmp_32.S | 25 and %o3, 0xff, %o0 41 and %o3, 0xff, %o0 57 and %o3, 0xff, %o0 73 and %o3, 0xff, %o0 93 and %o2, 3, %o2 98 and %o3, 0xff, %o0 117 and %g2, 0xff, %o0
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H A D | bitops.S | 19 and %o0, 63, %g2 27 and %g7, %o2, %g2 41 and %o0, 63, %g2 49 and %g7, %o2, %g2 63 and %o0, 63, %g2 71 and %g7, %o2, %g2 85 and %o0, 63, %g2 105 and %o0, 63, %g2 125 and %o0, 63, %g2
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/linux-master/arch/mips/include/asm/mach-ath79/ |
H A D | kernel-entry-init.h | 13 * and this cause performance issues. Let's go and change it to 19 and t0, t1
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/linux-master/arch/arm/mm/ |
H A D | abort-lv4t.S | 15 * abort here if the I-TLB and D-TLB aren't seeing the same 23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 33 and r7, r8, #15 << 24 67 and r6, r8, r7 68 and r9, r8, r7, lsl #1 70 and r9, r8, r7, lsl #2 72 and r9, r8, r7, lsl #3 76 and r6, r6, #15 @ r6 = no. of registers to transfer. 77 and r9, r8, #15 << 16 @ Extract 'n' from instruction 91 and r [all...] |
H A D | l2c-l2x0-resume.S | 34 @ The prefetch and power control registers are revision dependent 35 @ and can be written whether or not the L2 cache is enabled 37 and r0, r0, #L2X0_CACHE_ID_RTL_MASK
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H A D | abort-macro.S | 3 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb) 6 * during an abort the instructions will be treated as a write and the 18 and \tmp, \tmp, # 0xfe00 @ Mask opcode field 37 and \tmp, \insn, \tmp
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/linux-master/arch/mips/kernel/ |
H A D | entry.S | 2 * This file is subject to the terms and conditions of the GNU General Public 49 # between sampling and return 84 local_irq_disable # make sure need_resched and 86 # sampling and return 89 and t0, a2, t0 104 and v0, ST0_IEP 106 and v0, ST0_IE 128 local_irq_disable # make sure need_resched and 130 # sampling and return 138 work_notifysig: # deal with pending signals and [all...] |
H A D | relocate_kernel.S | 36 and s3, s2, 0x1 38 and s4, s2, ~0x1 /* store destination addr in s4 */ 43 and s3, s2, 0x2 45 and s0, s2, ~0x2 50 and s3, s2, 0x4 55 and s3, s2, 0x8 57 and s2, s2, ~0x8 104 * Other CPUs should wait until code is relocated and 114 /* Non-relocated address works for args and kexec_start_address ( old
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/linux-master/arch/arm/lib/ |
H A D | io-readsw-armv3.S | 43 and r3, r3, ip 48 and r4, r4, ip 53 and r5, r5, ip 58 and r6, r6, ip 74 and r3, r3, ip 79 and r4, r4, ip 89 and r3, r3, ip
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H A D | strchr.S | 15 and r1, r1, #0xff
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/linux-master/arch/arm/include/debug/ |
H A D | exynos.S | 7 /* pull in the relevant register and map files. */ 17 * aligned and add in the offset when we load the value here. 22 and \tmp, \tmp, #0xf0 26 and \tmp, \tmp, #0xf00
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/linux-master/arch/sparc/kernel/ |
H A D | getsetcc.S | 7 and %o1, 0xf, %o1 21 and %o2, %o3, %o2
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/linux-master/arch/mips/mm/ |
H A D | cex-gen.S | 2 * This file is subject to the terms and conditions of the GNU General Public 32 and k0,k0,k1
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/linux-master/arch/m68k/fpsp040/ |
H A D | x_operr.S | 10 | NAN is stored in the dest reg. If the dest format is b, w, or l and 13 | the dest format is integer (b, w, l) and the operr is caused by 21 | overflow -> OPERR, the exponent in wbte (and fpte) is: 28 | So, wbtemp and fptemp will contain the following on erroneously 93 | kernel handler. Set the operr bits and clean up, leaving 94 | only the integer exception frame on the stack, and the 116 bsr check_upper |check if exp and ms mant are special 121 bra not_enabled |clean and exit 163 bsr check_upper |check if exp and ms mant are special 168 bra not_enabled |clean and exi [all...] |
/linux-master/arch/mips/include/asm/mach-cavium-octeon/ |
H A D | kernel-entry-init.h | 2 * This file is subject to the terms and conditions of the GNU General Public 21 # addresses, and need to have the appropriate memory region set 40 # First clear off CvmCtl[IPPCI] bit and move the performance 43 and v0, v0, v1 47 and t1, v1, 0xfff8 50 and t1, v1, 0xfff8 53 and t1, v1, 0xfff8 56 and t1, v1, 0xff00 59 and t1, v1, 0x00ff 60 slti t1, t1, 2 # 66-P1.2 and late [all...] |
/linux-master/drivers/zorro/ |
H A D | zorro.ids | 8 # Manufacturers and Products. Please keep sorted. 22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion] 40 5000 A2620 68020 [Accelerator and RAM Expansion] 41 5100 A2630 68030 [Accelerator and RAM Expansion] 90 3900 Hurricane 2800 [Accelerator and RAM Expansion] 91 5700 Hurricane 2800 [Accelerator and RAM Expansion] 103 0500 500 [SCSI Host Adapter and RAM Expansion] 112 1100 Magnum 40 [Accelerator and SCSI Host Adapter] 118 0800 Impact Series I [SCSI Host Adapter and RAM Expansion] 127 1000 DKM 1202 [FPU and RA [all...] |
/linux-master/drivers/soc/bcm/brcmstb/pm/ |
H A D | s2-mips.S | 56 and t0, t1 59 and t2, t1 84 /* Enable CP0 interrupt 2 and wait for interrupt */ 90 and t0, t1 122 and t1, t0 145 and t0, t1 148 and t2, t1
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