/haiku/src/add-ons/accelerants/radeon/ |
H A D | GlobalData.c | 16 accelerator_info *ai; variable
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H A D | GlobalData.h | 15 extern accelerator_info *ai;
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H A D | InitAccelerant.c | 35 ai = malloc( sizeof( *ai )); 36 if( ai == NULL ) 39 memset( ai, 0, sizeof( *ai )); 41 ai->accelerant_is_clone = accelerant_is_clone; 42 ai->fd = the_fd; 47 result = ioctl( ai->fd, RADEON_GET_PRIVATE_DATA, &gpd, sizeof(gpd) ); 50 ai->virtual_card_area = clone_area( "Radeon virtual card", (void **)&ai [all...] |
H A D | CP.h | 52 //status_t Radeon_InitCP( accelerator_info *ai ); 54 int Radeon_AllocIndirectBuffer( accelerator_info *ai, bool keep_lock ); 55 void Radeon_FreeIndirectBuffer( accelerator_info *ai, 57 void Radeon_SendIndirectBuffer( accelerator_info *ai, 60 void Radeon_InvalidateStateBuffer( accelerator_info *ai, int state_buffer_idx ); 61 void Radeon_FreeIndirectBuffers( accelerator_info *ai ); 62 void Radeon_DiscardAllIndirectBuffers( accelerator_info *ai ); 65 static inline uint32 *Radeon_GetIndirectBufferPtr( accelerator_info *ai, int buffer_idx ) argument 67 return (uint32 *)(ai->mapped_memory[ai [all...] |
H A D | radeon_accelerant.h | 80 status_t Radeon_MoveDisplay( accelerator_info *ai, uint16 h_display_start, uint16 v_display_start ); 81 void Radeon_EnableIRQ( accelerator_info *ai, bool enable ); 87 void Radeon_InitMultiModeVars( accelerator_info *ai, display_mode *mode ); 100 status_t Radeon_SetDPMS( accelerator_info *ai, int crtc_idx, int mode ); 101 uint32 Radeon_GetDPMS( accelerator_info *ai, int crtc_idx ); 105 void Radeon_SetCursorColors( accelerator_info *ai, int crtc_idx ); 106 void Radeon_ShowCursor( accelerator_info *ai, int crtc_idx ); 110 void Radeon_Init2D( accelerator_info *ai ); 111 void Radeon_AllocateVirtualCardStateBuffer( accelerator_info *ai ); 112 void Radeon_FreeVirtualCardStateBuffer( accelerator_info *ai ); [all...] |
H A D | dpms.c | 25 virtual_card *vc = ai->vc; 31 result1 = Radeon_SetDPMS( ai, 0, dpms_flags ); 33 result1 = Radeon_SetDPMS( ai, 0, dpms_flags ); 52 return Radeon_GetDPMS( ai, ai->vc->used_crtc[0] ? 0 : 1 ); 57 static void Radeon_SetDPMS_LVDS( accelerator_info *ai, int mode ) argument 59 vuint8 *regs = ai->regs; 69 snooze( ai->si->panel_pwr_delay * 1000 ); 78 old_pixclks_cntl = Radeon_INPLL( ai->regs, ai 95 Radeon_SetDPMS_DVI( accelerator_info *ai, int mode ) argument 117 Radeon_SetDPMS_FP2( accelerator_info *ai, int mode ) argument 148 Radeon_SetDPMS_CRT( accelerator_info *ai, int mode ) argument 170 Radeon_SetDPMS_TVCRT( accelerator_info *ai, int mode ) argument 196 Radeon_SetDPMS_CRTC1( accelerator_info *ai, int mode ) argument 238 Radeon_SetDPMS_CRTC2( accelerator_info *ai, int mode ) argument 277 Radeon_SetDPMS_TVOUT( accelerator_info *ai, int mode ) argument 291 Radeon_SetDPMS( accelerator_info *ai, int crtc_idx, int mode ) argument 381 Radeon_GetDPMS( accelerator_info *ai, int crtc_idx ) argument [all...] |
H A D | palette.c | 22 accelerator_info *ai, int crtc_idx ) 26 if ( ai->si->acc_dma ) { 31 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) ); 40 Radeon_WaitForFifo ( ai , 1 ); 41 OUTREG( ai->regs, RADEON_DAC_CNTL2, 43 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) ); 45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 ); 47 Radeon_WaitForFifo ( ai , 1 ); // TODO FIXME good god this is gonna be slow... 48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i ); 54 accelerator_info *ai, in 21 Radeon_InitPalette( accelerator_info *ai, int crtc_idx ) argument 80 setPalette( accelerator_info *ai, int crtc_idx, uint count, uint8 first, uint8 *color_data ) argument [all...] |
H A D | Acceleration.c | 27 virtual_card *vc = ai->vc; 56 ++ai->si->engine.count; 66 virtual_card *vc = ai->vc; 70 Radeon_WaitForFifo ( ai , 1 ); 73 OUTREG(ai->regs, RADEON_DP_GUI_MASTER_CNTL, (vc->datatype << RADEON_GMC_DST_DATATYPE_SHIFT 84 Radeon_WaitForFifo ( ai , 4 ); 92 OUTREG(ai->regs, RADEON_DP_CNTL, ((xdir >= 0 ? RADEON_DST_X_LEFT_TO_RIGHT : 0) 96 OUTREG( ai->regs, RADEON_SRC_Y_X, (list->src_top << 16 ) | list->src_left); 97 OUTREG( ai->regs, RADEON_DST_Y_X, (list->dest_top << 16 ) | list->dest_left); 100 OUTREG( ai 413 Radeon_FillStateBuffer( accelerator_info *ai, uint32 datatype ) argument [all...] |
H A D | EngineManagment.c | 62 static void writeSyncToken( accelerator_info *ai ) 65 if( ai->si->engine.count == ai->si->engine.written ) 68 if( ai->si->acc_dma ) { 79 WRITE_IB_REG( RADEON_SCRATCH_REG0, ai->si->engine.count ); 81 ai->si->engine.written = ai->si->engine.count; 85 Radeon_WaitForFifo( ai, 2 ); 86 OUTREG( ai->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 87 OUTREG( ai [all...] |
H A D | driver_wrapper.c | 16 status_t Radeon_WaitForIdle( accelerator_info *ai, bool keep_lock ) argument 23 return ioctl( ai->fd, RADEON_WAITFORIDLE, &wfi, sizeof( wfi )); 28 status_t Radeon_WaitForFifo( accelerator_info *ai, int entries ) argument 34 int slots = INREG( ai->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK; 42 Radeon_ResetEngine( ai ); 48 void Radeon_ResetEngine( accelerator_info *ai ) 54 ioctl( ai->fd, RADEON_RESETENGINE, &na, sizeof( na )); 58 status_t Radeon_VIPRead( accelerator_info *ai, uint channel, uint address, uint32 *data ) argument 68 res = ioctl( ai->fd, RADEON_VIPREAD, &vr, sizeof( vr )); 77 status_t Radeon_VIPWrite( accelerator_info *ai, uint argument 90 Radeon_FindVIPDevice( accelerator_info *ai, uint32 device_id ) argument [all...] |
H A D | theatre_out.c | 107 accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) 110 Radeon_VIPWrite( ai, ai->si->theatre_channel, mapping->address, 121 accelerator_info *ai, uint16 addr ) 128 Radeon_VIPWrite( ai, ai->si->theatre_channel, 136 Radeon_VIPRead( ai, ai->si->theatre_channel, THEATRE_VIP_HOST_RD_WT_CNTL, &status ); 142 Radeon_VIPWrite( ai, ai 106 writeTheatreRegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 120 Radeon_TheatreReadFIFO( accelerator_info *ai, uint16 addr ) argument 150 Radeon_TheatreWriteFIFO( accelerator_info *ai, uint16 addr, uint32 value ) argument 179 Radeon_TheatreProgramTVRegisters( accelerator_info *ai, impactv_regs *values ) argument 220 readTheatreRegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 236 Radeon_TheatreReadTVRegisters( accelerator_info *ai, impactv_regs *values ) argument [all...] |
H A D | GetModeInfo.c | 21 virtual_card *vc = ai->vc; 40 virtual_card *vc = ai->vc; 56 uint32 clock_limit = ai->si->pll.max_pll_freq * 10; 73 fp_info *fpInfo = &ai->si->flatpanels[0]; 74 disp_entity* routes = &ai->si->routing; 82 if ((ai->vc->connected_displays & (dd_dvi | dd_dvi_ext | dd_lvds)) == 0) 87 for (i = 0; i < ai->si->mode_count; ++i) { 88 if (ai->mode_list[i].timing.h_display == fpInfo->panel_xres 89 && ai->mode_list[i].timing.v_display == fpInfo->panel_yres 90 && ai [all...] |
H A D | Cursor.c | 17 static void moveOneCursor( accelerator_info *ai, int crtc_idx, int x, int y ); 20 void Radeon_SetCursorColors( accelerator_info *ai, int crtc_idx ) argument 25 OUTREG( ai->regs, RADEON_CUR_CLR0, 0xffffff ); 26 OUTREG( ai->regs, RADEON_CUR_CLR1, 0 ); 28 OUTREG( ai->regs, RADEON_CUR2_CLR0, 0xffffff ); 29 OUTREG( ai->regs, RADEON_CUR2_CLR1, 0 ); 37 virtual_card *vc = ai->vc; 72 virtual_card *vc = ai->vc; 79 ACQUIRE_BEN( ai->si->engine.lock ); 109 Radeon_MoveDisplay( ai, hd 151 moveOneCursor( accelerator_info *ai, int crtc_idx, int x, int y ) argument 220 Radeon_ShowCursor( accelerator_info *ai, int crtc_idx ) argument [all...] |
H A D | CP.c | 50 static uint getAvailRingBuffer( accelerator_info *ai ) 52 CP_info *cp = &ai->si->cp; 56 *(uint32 *)(ai->mapped_memory[cp->feedback.mem_type].data + cp->feedback.head_mem_offset) 59 //space = INREG( ai->regs, RADEON_CP_RB_RPTR ) - cp->ring.tail; 69 *(uint32 *)(ai->mapped_memory[cp->feedback.mem_type].data + cp->feedback.head_mem_offset), 83 void Radeon_FreeIndirectBuffers( accelerator_info *ai ) 85 CP_info *cp = &ai->si->cp; 87 ((uint32 *)(ai->mapped_memory[cp->feedback.mem_type].data + cp->feedback.scratch_mem_offset))[1]; 88 //ai->si->cp.scratch.ptr[1]; 89 //INREG( ai 169 Radeon_AllocIndirectBuffer( accelerator_info *ai, bool keep_lock ) argument 201 Radeon_FreeIndirectBuffer( accelerator_info *ai, int buffer_idx, bool never_used ) argument 267 Radeon_SendIndirectBuffer( accelerator_info *ai, int buffer_idx, int buffer_size, int state_buffer_idx, int state_buffer_size, bool has_lock ) argument 361 Radeon_InvalidateStateBuffer( accelerator_info *ai, int state_buffer_idx ) argument 381 Radeon_WaitForRingBufferSpace( accelerator_info *ai, uint num_dwords ) argument [all...] |
H A D | monitor_detection.c | 30 accelerator_info *ai; member in struct:__anon1 40 vuint8 *regs = info->ai->regs; 56 vuint8 *regs = info->ai->regs; 74 Radeon_ReadEDID(accelerator_info *ai, uint32 ddcPort, edid1_info *edid) argument 81 info.ai = ai; 102 Radeon_DetectCRTInt(accelerator_info *ai, bool colour) argument 104 vuint8 *regs = ai->regs; 153 Radeon_DetectCRT(accelerator_info *ai) argument 159 old_vclk_ecp_cntl = Radeon_INPLL(ai 178 Radeon_DetectTVCRT_RV200(accelerator_info *ai) argument 229 Radeon_DetectTVCRT_R300(accelerator_info *ai) argument 291 Radeon_DetectTVCRT(accelerator_info *ai) argument 332 Radeon_DetectTV_RV200(accelerator_info *ai, bool tv_crt_found) argument 417 Radeon_DetectTV_R300(accelerator_info *ai) argument 500 readTVDetect(accelerator_info *ai) argument 556 Radeon_DetectTV_Theatre(accelerator_info *ai) argument 662 Radeon_DetectTV(accelerator_info *ai, bool tv_crt_found) argument 812 Radeon_StoreFPEDID(accelerator_info *ai, int port, const edid1_info *edid) argument 845 Radeon_ConnectorInfo(accelerator_info *ai, int port, disp_entity* ptr_entity) argument 907 Radeon_DetectDisplays(accelerator_info *ai) argument [all...] |
H A D | internal_tv_out.c | 91 accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) 93 vuint8 *regs = ai->regs; 108 accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) 114 Radeon_OUTPLL( ai->regs, ai->si->asic, 127 accelerator_info *ai, uint16 addr ) 129 vuint8 *regs = ai->regs; 159 accelerator_info *ai, uint16 addr, uint32 value ) 161 vuint8 *regs = ai->regs; 164 //readFIFO( ai, add 90 writeMMIORegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 107 writePLLRegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 158 Radeon_InternalTVOutWriteFIFO( accelerator_info *ai, uint16 addr, uint32 value ) argument 187 Radeon_InternalTVOutProgramRegisters( accelerator_info *ai, impactv_regs *values ) argument 230 readMMIORegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 248 readPLLRegList( accelerator_info *ai, impactv_regs *values, const register_mapping *mapping ) argument 264 Radeon_InternalTVOutReadRegisters( accelerator_info *ai, impactv_regs *values ) argument [all...] |
H A D | flat_panel.c | 21 accelerator_info *ai, fp_regs *values ) 23 vuint8 *regs = ai->regs; 108 accelerator_info *ai, fp_regs *values ) 110 vuint8 *regs = ai->regs; 118 accelerator_info *ai, fp_regs *values ) 120 vuint8 *regs = ai->regs; 135 if (ai->si->asic == rt_rv280) { 148 accelerator_info *ai, crtc_info *crtc, 187 if (ai->si->tmds_pll[i].freq == 0) 189 if ((uint32)(fp_port->dot_clock) < ai 20 Radeon_ReadRMXRegisters( accelerator_info *ai, fp_regs *values ) argument 107 Radeon_ProgramRMXRegisters( accelerator_info *ai, fp_regs *values ) argument 117 Radeon_ReadFPRegisters( accelerator_info *ai, fp_regs *values ) argument 147 Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc, fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values ) argument 249 Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc, fp_info *fp_port, fp_regs *values ) argument [all...] |
H A D | set_mode.h | 208 void Radeon_CalcCRTCRegisters( accelerator_info *ai, crtc_info *crtc, 210 void Radeon_ProgramCRTCRegisters( accelerator_info *ai, int crtc_idx, 217 void Radeon_ProgramPLL( accelerator_info *ai, int crtc_idx, pll_regs *values ); 233 void Radeon_ReadRMXRegisters( accelerator_info *ai, fp_regs *values ); 235 void Radeon_ProgramRMXRegisters( accelerator_info *ai, fp_regs *values ); 237 void Radeon_ReadFPRegisters( accelerator_info *ai, fp_regs *values ); 238 void Radeon_CalcFPRegisters( accelerator_info *ai, crtc_info *crtc, 240 void Radeon_ProgramFPRegisters( accelerator_info *ai, crtc_info *crtc, 246 accelerator_info *ai, routing_regs *values ); 248 accelerator_info *ai, cons [all...] |
H A D | SetDisplayMode.c | 40 accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params ); 84 accelerator_info *ai ) 86 vuint8 *regs = ai->regs; 107 accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params ) 109 virtual_card *vc = ai->vc; 110 shared_info *si = ai->si; 111 vuint8 *regs = ai->regs; 202 Radeon_WaitForIdle( ai, true ); 206 Radeon_ReadRMXRegisters( ai, &fp_values ); 208 Radeon_ReadFPRegisters( ai, 106 Radeon_SetMode( accelerator_info *ai, crtc_info *crtc, display_mode *mode, impactv_params *tv_params ) argument 318 Radeon_EnableIRQ( accelerator_info *ai, bool enable ) argument [all...] |
H A D | monitor_routing.c | 27 accelerator_info *ai, routing_regs *values ) 29 vuint8 *regs = ai->regs; 36 values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL ); 37 values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL ); 39 switch( ai->si->asic ) { 66 if( ai->si->asic > rt_r100 ) { 71 if( IS_INTERNAL_TV_OUT( ai->si->tv_chip )) 81 accelerator_info *ai, cons 26 Radeon_ReadMonitorRoutingRegs( accelerator_info *ai, routing_regs *values ) argument 80 Radeon_CalcMonitorRouting( accelerator_info *ai, const impactv_params *tv_parameters, routing_regs *values ) argument 419 Radeon_ProgramMonitorRouting( accelerator_info *ai, routing_regs *values ) argument 544 assignDefaultMonitorRoute( accelerator_info *ai, display_device_e display_devices, int whished_num_heads, bool use_laptop_panel, display_device_e *crtc1, display_device_e *crtc2 ) argument 650 Radeon_SetupDefaultMonitorRouting( accelerator_info *ai, int whished_num_heads, bool use_laptop_panel ) argument [all...] |
/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | agp.c | 14 static void agp_list_info(agp_info ai); 92 agp_list_info(agp_info ai) argument 97 if (ai.class_base == PCI_display) { 98 SHOW_INFO(4, "Device is a graphics card, subclass ID is $%02x", ai.class_sub); 100 SHOW_INFO(4, "Device is a hostbridge, subclass ID is $%02x", ai.class_sub); 103 SHOW_INFO(4, "Vendor ID $%04x", ai.vendor_id); 104 SHOW_INFO(4, "Device ID $%04x", ai.device_id); 105 SHOW_INFO(4, "Bus %d, device %d, function %d", ai.bus, ai.device, ai [all...] |
/haiku/src/bin/ |
H A D | catarea.c | 8 area_info ai; local 17 get_area_info(cloned, &ai); 18 //fprintf(stderr, "copy of bios: size=0x%08lx\n", ai.size); 19 write(1, ptr, ai.size);
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/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | agp.c | 10 static void eng_agp_list_info(agp_info ai); 136 static void eng_agp_list_info(agp_info ai) argument 141 if (ai.class_base == PCI_display) 142 LOG(4,("AGP: device is a graphicscard, subclass ID is $%02x\n", ai.class_sub)); 144 LOG(4,("AGP: device is a hostbridge, subclass ID is $%02x\n", ai.class_sub)); 145 LOG(4,("AGP: vendor ID $%04x\n", ai.vendor_id)); 146 LOG(4,("AGP: device ID $%04x\n", ai.device_id)); 147 LOG(4,("AGP: bus %d, device %d, function %d\n", ai.bus, ai.device, ai [all...] |
/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_agp.c | 10 static void nv_agp_list_info(agp_info ai); 141 nv_agp_list_info(agp_info ai) argument 146 if (ai.class_base == PCI_display) 147 LOG(4,("AGP: device is a graphicscard, subclass ID is $%02x\n", ai.class_sub)); 149 LOG(4,("AGP: device is a hostbridge, subclass ID is $%02x\n", ai.class_sub)); 150 LOG(4,("AGP: vendor ID $%04x\n", ai.vendor_id)); 151 LOG(4,("AGP: device ID $%04x\n", ai.device_id)); 152 LOG(4,("AGP: bus %d, device %d, function %d\n", ai.bus, ai.device, ai [all...] |
/haiku/src/tests/system/network/multicast/ |
H A D | multicat.c | 216 struct addrinfo hints, *res, *ai; local 227 for (ai = res; ai; ai = ai->ai_next) { 228 if ((fd = socket(ai->ai_family, ai->ai_socktype, ai->ai_protocol)) < 0) 232 if (bind(fd, ai->ai_addr, ai [all...] |