Searched refs:ack_mask (Results 1 - 24 of 24) sorted by relevance

/linux-master/include/linux/soc/actions/
H A Dowl-sps.h9 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
/linux-master/drivers/pmdomain/actions/
H A Dowl-sps-helper.c17 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable) argument
24 ack = val & ack_mask;
37 if ((val & ack_mask) == (enable ? ack_mask : 0))
H A Dowl-sps.c51 u32 pwr_mask, ack_mask; local
53 ack_mask = BIT(pd->info->ack_bit);
56 return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
/linux-master/drivers/gpu/drm/amd/display/dc/irq/
H A Dirq_service.h53 uint32_t ack_mask; member in struct:irq_source_info
H A Dirq_service.c137 value = (value & ~info->ack_mask) |
138 (info->ack_value & info->ack_mask);
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c98 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK,\
112 .ack_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK,\
126 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
141 .ack_mask =\
157 .ack_mask =\
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce60/
H A Dirq_service_dce60.c110 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
124 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
139 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
154 .ack_mask =\
170 .ack_mask =\
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce80/
H A Dirq_service_dce80.c101 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\
115 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\
130 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\
145 .ack_mask =\
161 .ack_mask =\
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c218 .ack_mask = \
232 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c216 REG_STRUCT[base + reg_num].ack_mask = \
230 REG_STRUCT[base].ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c224 .ack_mask = \
238 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
222 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c229 .ack_mask = \
243 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c217 .ack_mask = \
231 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c219 .ack_mask = \
233 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c222 .ack_mask = \
236 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c195 REG_STRUCT[base + reg_num].ack_mask = \
209 REG_STRUCT[base].ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c161 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c146 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c209 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c112 .ack_mask = \
/linux-master/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c212 .ack_mask = \
/linux-master/drivers/pmdomain/rockchip/
H A Dpm-domains.c44 int ack_mask; member in struct:rockchip_domain_info
112 .ack_mask = (ack), \
125 .ack_mask = (ack), \
143 .ack_mask = (ack), \
152 .ack_mask = (ack), \
327 target_ack = idle ? pd_info->ack_mask : 0;
329 (val & pd_info->ack_mask) == target_ack,
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c4615 u32 reg_base, val, ack_mask, timeout_usec = 100000; local
4622 ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_RUN_ACK_MASK;
4624 ack_mask = ARC_FARM_ARC0_AUX_RUN_HALT_ACK_HALT_ACK_MASK;
4627 val, ((val & ack_mask) == ack_mask),

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