/linux-master/arch/mips/sgi-ip22/ |
H A D | ip22-nvram.c | 36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ 37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ 40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ 41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ 47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ 48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 64 __raw_writel(__raw_readl(ctr [all...] |
/linux-master/arch/arm/mach-pxa/ |
H A D | smemc.c | 23 msc[0] = __raw_readl(MSC0); 24 msc[1] = __raw_readl(MSC1); 25 sxcnfg = __raw_readl(SXCNFG); 26 memclkcfg = __raw_readl(MEMCLKCFG); 27 csadrcfg[0] = __raw_readl(CSADRCFG0); 28 csadrcfg[1] = __raw_readl(CSADRCFG1); 29 csadrcfg[2] = __raw_readl(CSADRCFG2); 30 csadrcfg[3] = __raw_readl(CSADRCFG3); 78 unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
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/linux-master/arch/sh/boards/mach-dreamcast/ |
H A D | rtc.c | 39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | 40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); 42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | 43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); 71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | 72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); 74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | 75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
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/linux-master/arch/mips/bmips/ |
H A D | dma.c | 24 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 26 __raw_readl(cbr + BMIPS_RAC_CONFIG);
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/linux-master/arch/arm/boot/compressed/ |
H A D | misc-ep93xx.h | 8 static inline unsigned int __raw_readl(unsigned int ptr) function 37 v = __raw_readl(PHYS_ETH_SELF_CTL); 41 while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
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/linux-master/arch/sh/include/asm/ |
H A D | mmu_context_32.h | 13 return __raw_readl(MMU_PTEAEX) & MMU_CONTEXT_ASID_MASK; 49 return (pgd_t *)__raw_readl(MMU_TTB);
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/linux-master/arch/mips/alchemy/common/ |
H A D | usb.c | 102 r = __raw_readl(base + USB_DWC_CTRL2); 103 s = __raw_readl(base + USB_DWC_CTRL3); 131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ 139 r = __raw_readl(base + USB_INT_ENABLE); 148 r = __raw_readl(base + USB_INT_ENABLE); 153 r = __raw_readl(base + USB_DWC_CTRL3); 168 r = __raw_readl(base + USB_DWC_CTRL3); 173 r = __raw_readl(base + USB_DWC_CTRL1); 180 r = __raw_readl(base + USB_INT_ENABLE); 185 r = __raw_readl(bas [all...] |
/linux-master/arch/mips/loongson32/common/ |
H A D | irq.c | 28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) 37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) 46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) 48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) 57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) 68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) 70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) 74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) 76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) 80 __raw_writel(__raw_readl(LS1X_INTC_INTPO [all...] |
/linux-master/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7770.c | 21 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; 30 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); 40 int idx = (__raw_readl(FRQCR) & 0x000f); 50 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
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H A D | clock-sh7780.c | 24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; 33 int idx = (__raw_readl(FRQCR) & 0x0003); 43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); 76 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
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H A D | ubc.c | 50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, 59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, 69 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) 77 return __raw_readl(UBC_CCMFR); 82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); 121 (void)__raw_readl(UBC_CRR(i));
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H A D | smp-shx3.c | 34 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ 51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); 91 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) 94 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) 103 return __raw_readl(0xff000048); /* CPIDR */ 118 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
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H A D | clock-sh7763.c | 24 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; 33 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); 43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); 70 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
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H A D | intc-shx3.c | 18 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
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/linux-master/arch/arm/mach-s3c/ |
H A D | pm-core-s3c64xx.h | 30 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
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H A D | pm-gpio.c | 29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); 30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); 36 u32 old_gpcon = __raw_readl(base + OFFS_CON); 37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); 66 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); 67 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); 68 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); 123 u32 old_gpcon = __raw_readl(base + OFFS_CON); 124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); 194 chip->pm_save[1] = __raw_readl(chi [all...] |
H A D | wakeup-mask.c | 23 val = __raw_readl(reg); 40 printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val);
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/linux-master/arch/sh/kernel/cpu/sh3/ |
H A D | probe.c | 30 data0 = __raw_readl(addr0); 32 data1 = __raw_readl(addr1); 36 data0 = __raw_readl(addr0); 39 data1 = __raw_readl(addr1); 42 data3 = __raw_readl(addr0);
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/linux-master/arch/mips/include/asm/mach-rc32434/ |
H A D | dma_v.h | 29 if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { 32 if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
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/linux-master/arch/sh/lib/ |
H A D | io.c | 19 *data++ = __raw_readl(addr); 59 *data++ = __raw_readl(addr);
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/linux-master/arch/mips/include/asm/mach-ralink/ |
H A D | ralink_regs.h | 42 return __raw_readl(rt_sysc_membase + reg); 59 return __raw_readl(rt_memc_membase + reg);
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/linux-master/drivers/irqchip/ |
H A D | irq-ath79-misc.c | 41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & 42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 92 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); 96 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
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/linux-master/arch/sh/boards/mach-sh7763rdp/ |
H A D | irq.c | 31 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
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/linux-master/drivers/tty/serial/ |
H A D | apbuart.h | 53 #define UART_GET_CHAR(port) (__raw_readl(APBBASE_DATA_P(port))) 55 #define UART_GET_STATUS(port) (__raw_readl(APBBASE_STATUS_P(port))) 57 #define UART_GET_CTRL(port) (__raw_readl(APBBASE_CTRL_P(port))) 59 #define UART_GET_SCAL(port) (__raw_readl(APBBASE_SCALAR_P(port)))
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/linux-master/arch/mips/kernel/ |
H A D | gpio_txx9.c | 21 return !!(__raw_readl(&txx9_pioptr->din) & (1 << offset)); 27 val = __raw_readl(&txx9_pioptr->dout); 49 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), 62 __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset),
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