Searched refs:XCHAL_DCACHE_LINEWIDTH (Results 1 - 10 of 10) sorted by last modified time

/linux-master/arch/xtensa/include/asm/
H A Dcache.h16 #define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
22 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
H A Dcacheasm.h87 XCHAL_DCACHE_LINEWIDTH 240
107 XCHAL_DCACHE_LINEWIDTH 240
117 XCHAL_DCACHE_LINEWIDTH 240
127 XCHAL_DCACHE_LINEWIDTH 1020
147 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
156 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
165 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
184 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
193 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
202 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 102
[all...]
/linux-master/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h212 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/csp/include/variant/
H A Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 6 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h183 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h132 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/de212/include/variant/
H A Dcore.h211 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h124 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h163 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ macro
/linux-master/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h117 #define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ macro

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